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rev. 2.3 - may 2004 1/137 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. preliminary data st52f510/f513/f514 8-bit intelligent controller unit (icu) two timer/pwms, adc, i 2 c, spi, sci ? memories up to 8 kbytes single voltage flash memory 256 bytes of register file 256 bytes of ram up to 4 kbytes data eeprom in situ programming in flash devices (isp) single byte and page modes and in application programming for writing data in flash memory readout protection and flexible write protection core register file based architecture 107 basic instructions hardware multiplication and division decision processor for the implementation of fuzzy logic algorithms deep system and user stacks clock and power supply up to 20 mhz clock frequency programmable oscillator modes: ? 10 mhz internal oscillator ? external clock/ oscillator power-on reset (por) programmable low voltage detector (plvd) with 3 configurable thresholds power saving features interrupts 8 interrupt vectors with one sw trap non-maskable interrupt (nmi) two port interrupts with up to 16 sources i/o ports from 10 up to 22 i/o pins configurable in pull- up, push-pull, weak pull-up, open-drain and high-impedance high current sink/source in all pins peripherals on-chip 10-bit a/d converter with 8 channel analog multiplexer and autocalibration. 2 programmable 16 bit timer/pwms with internal 16-bit prescaler featuring: ? pwm output ? input capture ? output compare ? pulse generator mode watchdog timer serial communication interface (sci) with asynchronous protocol (uart). i 2 c ? peripheral with master and slave mode 3-wire spi ? peripheral supporting single master and multi master spi modes development tools high level software tools ? c ? compiler emulator low cost programmer gang programmer lfbga36 st52f510/f513/f514
2/137 table of contents st52f510/f513/f514 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.2.1 memory programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.2 working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2 internal architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 control unit and data processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1.1 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1.2 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3 addressing spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.2 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.3 program/data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.4 system and user stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.5 input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.6 output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.7 configuration registers & option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.8 fuzzy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4 memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 program/data memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.2 memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.2.1 programming mode start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.2 fast programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.3 random data writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.4 option bytes programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 memory verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.3.1 fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.2 random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4 memory lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5 id code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.6 error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.7 in-situ programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.8 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.8.1 single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8.2 block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8.3 memory corruption prevention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8.4 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.8.5 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents
st52f510/f513/f514 3/137 5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.2 global interrupt request enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.4 interrupt maskability and priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5 interrupt reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6 clock, reset & power saving modes . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.2.1 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2.2 reset procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3 programmable low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.4.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.1 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.2 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.3 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.4 interrupt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7.6.1 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.6.2 input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6.3 output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8 fuzzy computation (dp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1 fuzzy inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.2 fuzzyfication phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.3 inference phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.4 defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.5 input membership function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.6 output singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.7 fuzzy rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 9 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 9.2 instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 10 10-bit a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
st52f510/f513/f514 4/137 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 10.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 10.3.1 one channel single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.2 multiple channels single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 10.3.3 one channel continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.4 multiple channels continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.5 a/d converter register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.5.1 a/d converter configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.5.2 input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 12 pwm/timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.2 timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.3 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 12.3.1 simultaneous start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.4 timer interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 12.5 pwm/timer 0 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 12.5.1 pwm/timer 0 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.5.2 pwm/timer 0 input registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.5.3 pwm/timer 0 output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.6 pwm/timer 1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 12.6.1 pwm/timer 1 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.6.2 pwm/timer 1 input registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.6.3 pwm/timer 1 output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13 serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.1 sci receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 13.1.1 recovery buffer block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.1.2 scdr_rx block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.2 sci transmitter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 13.3 baud rate generator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 13.4 sci register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 13.4.1 sci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.4.2 sci input registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.4.3 sci output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 14.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 14.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
st52f510/f513/f514 5/137 14.3.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.3.2 communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.3.3 sda/scl line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 14.4.1 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.2 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 14.5.1 i2c interface configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.5.2 i2c interface input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.5.3 i2c interface output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 15 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 15.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 15.3 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 15.4.1 master configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 15.4.2 slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.4.3 data transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.4.4 write collision error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.4.5 master mode fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 15.4.6 overrun condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.4.7 single master and multimaster configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.4.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 15.5 spi register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 15.5.1 spi configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 15.5.2 spi input register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 15.5.3 spi output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 16 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 16.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.2 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.3 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 16.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 16.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 16.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 16.6 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 16.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 16.8 programmable low voltage detector (plvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 16.9 internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
st52f510/f513/f514 6/137 16.10 port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 16.10.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16.10.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 16.11 control pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.11.1 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 16.11.2 vpp pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 16.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 16.12.1 functional ems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.12.2 absolute electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.12.3 electro-static discharge (esd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.12.4 static and dynamic latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 16.12.5 esd pin protection strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 22 16.13 i2c interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 16.14 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 16.15 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 17 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17.1 so16 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 17.2 so20 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 17.3 pdip20 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 17.4 so28 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 17.5 sdip32 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 17.6 lfbga36 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 18 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 18.1 silicon identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 18.2 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 18.2.1 eeprom writing error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 18.2.2 cpu prescaler after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 18.2.3 sci synchronization in case of consecutive bytes reception . . . . . . . . . . . . . . . . . . . . . 135 18.2.4 i2c general call flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 18.2.5 halt not skipped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
st52f510/f513/f514 7/137 1 general description 1.1 introduction st52f510/f513/f514 are devices of st five family of 8-bit intelligent controller units (icu), which can perform, both boolean and fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. produced by stmicroelectronics using the reliable high performance cmos process for single voltage flash versions, st52f510/f513/f514 include integrated on-chip peripherals that allow maximization of system reliability, and decreased system costs in order to minimize the number of external components. the flexible i/o configuration of st52f510/f513/ f514 allow one to interface with a wide range of external devices (for example d/a converters or power control devices), and to communicate with the most common serial standards. st52f510/f513/f514 pins are configurable. the user can set input or output signals on each single pin in 8 different modes, reducing the need for external components in order to supply a suitable interface with the port pins. a hardware multiplier and divider, together with a wide instruction set, allow the implementation of complex functions by using a single instruction. therefore, program memory utilization and computational speed is optimized. fuzzy logic dedicated structures in st52f510/ f513/f514 icu ? s can be exploited to model complex system with high accuracy in a useful and simple manner. fuzzy expert systems for overall system management and fuzzy real time controls can be designed to increase performance at competitive costs. the linguistic approach characterizing fuzzy logic is based on a set of if-then rules, which describe the control behavior and on membership functions associated with input and output variables. up to 340 membership functions, with triangular and trapezoidal shapes, or singleton values are available to describe fuzzy variables. the timer/pwm peripheral allows one to manage power devices and timing signals, by implementing different operating modes and high frequency pwm (pulse width modulation) controls. input capture and output compare functions are available on the timers. the timer has a 16-bit programmable internal prescaler and a 16-bit counter, which can use internal or external start/stop signals and clock. an internal programmable watchdog is available to avoid loop errors and reset the icu. st52f510/f513/f514 includes a 10-bit, self- calibrating, analog to digital converter with an 8- analog channel multiplexer. single/multiple channels and single/sequence conversion modes are supported. external reference can be supplied to obtain more stability and precision in the conversion. st52f510/f513/f514 supply different peripherals to implement the most common serial communication protocols. sci allows the performance of serial asynchronous communication (uart). i 2 c and spi peripherals allow the implementation of synchronous serial protocols. i 2 c peripherals can work both in master and slave mode. spi implements single and multi master modes using 3-wire. up to 8 interrupt vectors are available, which allow synchronization with peripherals and external devices. non-maskable interrupt and s/w trap are available. all interrupts have configurable priority levels and are maskable excluding the non-maskable interrupt, which has fixed top level priority. two versatile port interrupts are available for synchronization with external sources. the st52f510/f513/f514 also include an on-chip power-on-reset (por), which provides an internal chip reset during power up situation and a programmable low voltage detector (plvd), which causes the icu to reset if the voltage source v dd dips below a threshold. three programmable thresholds are available, allowing to work with different supply voltages (from 2.7 to 5.5 v). in order to optimize energy consumption, two different power saving modes are available: wait mode and halt mode. internal oscillator at 10 mhz 1% is available. external clock or quartz oscillator are also applicable. the device always starts with the internal oscillator, then it reads an option byte where the clock mode to be used is programmed. program memory addressing capability addresses up to 8 kbytes of memory location to store both program instructions and data. memory can be locked by the user in order to prevent external undesired operations. operations may be performed on data stored in ram, allowing direct combination of new inputs and feedback data. all ram bytes are used like register file. an additional ram bench is added to the program memory addressing space in order to allow the management of the system/user stacks and user data storage.
st52f510/f513/f514 8/137 st52f510/f513/f514 supply the system stack and the user stack located in the additional ram bench. the user stack can be located anywhere in the additional ram by writing the top address in the configuration registers, in order to avoid overlap with other data. single voltage flash allows the user to reprogram the devices on-board by means of the in situ programming (isp) feature. it is possible to store in safe way up to 4k of data in the available eeprom memory benches. permanent data, both in flash and eeprom can be managed by means of the in-application-programming (iap) feature. single byte and page write modes are supported. flexible write protection, of permanent data or program instructions, is also available. the instruction set composed of up to 107 instructions allows code compression and high speed in the program implementation. a powerful development environment consisting of a board and software tools allows an easy configuration and use of st52f510/f513/f514. the visual five software tool allows the development and debugging of projects via a user- friendly graphical interface and optimization of generated microcode. third-party hardware emulators and ? c ? compiler are available to speed-up the application implementation and time-to-market. 1.2 functional description st52f510/f513/f514 icu ? s can work in two modes according to the vpp signal levels: memory programming mode working mode during working mode vpp must be tied to vss. to enter the memory programming mode, the vpp pin must be tied to vdd. a reset signal must be applied to the device to switch from one mode to the other. 1.2.1 memory programming mode. the st52f510/f513/f514 memory is loaded in the memory programming mode. all instructions and data are written inside the memory during this phase. the user option bytes are loaded during this phase by using the programming tools. the option bytes can only be loaded in this phase and cannot be modified run-time. data and commands are transmitted by using the i 2 c protocol, implemented using the internal i 2 c peripheral. the in-situ programming protocol (isp) uses the following pins: sda and scl for transmission vpp for entering in the mode reset for starting the protocol in a stable status vdd and vss for the power supply. the internal clock is used in this phase. 1.2.2 working mode. the processor starts the working phase following the instructions, which have been previously loaded in the first locations of the memory. the first instruction must be a jump to the first program instruction, skipping the data (interrupt vectors, membership functions, user data) stored in the first memory page. st52f510/f513/f514 ? s internal structure includes two computational blocks, the control unit (cu) and the data processing unit (dpu), which performs boolean functions. the decision processor (dp) block cooperates with these blocks to perform fuzzy algorithms. the dp can manage up to 340 different membership functions for the antecedent part of fuzzy rules. the consequent terms of the rules are ? crisp ? values (real numbers). the maximum number of rules that can be defined is limited by the dimensions of the standard algorithm implemented. the program/data memory is shared between fuzzy and standard algorithms. within this memory, the user data can be stored both in non volatile memory as well as in the ram locations. the control unit (cu) reads information and the status of the peripherals. arithmetic calculus can be performed on these values by using the internal cu and register file, which supports all computations. the peripheral inputs can be fuzzy and/or arithmetic output values contained in the register file or program/ data memory.
st52f510/f513/f514 9/137 legend: table 1.1 st52f510/f513/f514 devices summary device nvm rf ram eeprom timers adc comms i/o package st52f510ymm6 4/8 k flash 256 256 - 2x16-bit 10-bit 2 ch sci i 2 c 10 so 16 st52f510fmm6 4/8 k flash 256 256 - 2x16-bit 10-bit 6 ch sci i 2 c 14 so 20 st52f510fmb6 4/8 k flash 256 256 - 2x16-bit 10-bit 6 ch sci i 2 c 14 dip 20 st52f510gmm6 4/8 k flash 256 256 - 2x16-bit 10-bit 8 ch sci i 2 c spi 22 so 28 st52f510kmb6 4/8 k flash 256 256 - 2x16-bit 10-bit 8 ch sci i 2 c spi 22 sdip 32 st52f513ymm6 4/8 k flash 256 256 256 2x16-bit 10-bit 2 ch sci i 2 c 10 so 16 st52f513fmm6 4/8 k flash 256 256 256 2x16-bit 10-bit 6 ch sci i 2 c 14 so 20 st52f513fmb6 4/8 k flash 256 256 256 2x16-bit 10-bit 6 ch sci i 2 c 14 dip 20 st52f513gmm6 4/8 k flash 256 256 256 2x16-bit 10-bit 8 ch sci i 2 c spi 22 so 28 st52f513kmb6 4/8 k flash 256 256 256 2x16-bit 10-bit 8 ch sci i 2 c spi 22 sdip 32 st52f514fmm6 4 k flash 256 256 1024 / 4096 2x16-bit 10-bit 6 ch sci i 2 c 14 so 20 st52f514fmb6 4 k flash 256 256 1024 / 4096 2x16-bit 10-bit 6 ch sci i 2 c 14 dip 20 st52f514gmm6 4 k flash 256 256 1024 / 4096 2x16-bit 10-bit 8 ch sci i 2 c spi 22 so 28 st52f514kmb6 4 k flash 256 256 1024 / 4096 2x16-bit 10-bit 8 ch sci i 2 c spi 22 sdip 32 st52f513g3h6 8 k flash 256 256 256 2x16-bit 10-bit 8 ch sci i 2 c spi 22 lfbga36 common features st52f510/f513/f514 watchdog yes other features nmi, plvd, por, isp, iap, internal oscillator temperature range from -40 to +85 operating supply 2.7 - 5.5 v cpu frequency from 1 to 20 mhz. sales code: st52tnnncmpy memory type (t): f=flash subfamily (nnn): 510, 513, 514 pin count (c): y=16 pins, f=20 pins, g=28/36 pins, k=32/34 pins memory size (m): 2=4 kb, 3=8 kb flash (st52f510 & st52f513) 1=1024, 3=4096 eeprom (only st52f514) packages (p): b=pdip/sdip, m=pso, h=lfgba temperature (y): 0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105
st52f510/f513/f514 10/137 figure 1.1 st52f510/f513/f514 block diagram port a timer/pwm 0 port c timer/pwm 1 i 2 c pa7:0 spi pc5:0 port b pb7:0 adc watchdog core decision processor control unit register file 256 bytes input registers pc flags power supply & plvd power on reset oscillator vdd vpp vss oscin oscout reset alu & dpu sci memory flash isp/iap data ram 256 bytes data eeprom memory interface
st52f510/f513/f514 11/137 figure 1.2 st52f510/f513/f514 so20/dip20 pin configuration figure 1.3 st52f510/f513/f514 so16 pin configuration vdd oscout oscin vpp vss reset pa0/scl pa1/sda pa2/t1out pa3/rx pa4/tstrt pa5/tclk/tx pa6/t0out pa7/int 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdd oscout oscin vpp vss reset pa0/scl pa1/sda pa2/t1out pa3/rx pa4/tstrt pa5/tclk/tx pa6/t0out pa7/int 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 so20 dip20 pb0/vref/ain0 pb1/ain1 pb2/ain2 pb3/ain3 pb4/ain4 pb5/ain5 pb0/vref/ain0 pb1/ain1 pb2/ain2 pb3/ain3 pb4/ain4 pb5/ain5 vdd oscout oscin vpp pb0/vref/ain0 pb1/ain1 pa7/int pa6/t0out vss reset pa0/scl pa1/sda pa2/t1out pa3/rx pa4/tstrt pa5/tclk/tx 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 so16
st52f510/f513/f514 12/137 figure 1.4 st52f510/f513/f514 sdip32/dip28 pin configuration figure 1.5 st52f510/f513/f514 lfbga36 pin configuration (view through package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 sdip32 vss reset pa0/scl pa1/sda pa2/t1out pa3/rx pa4/tstrt pa6/t0out pa7/int pc5/tres pc4/tx pc3/ss pc2miso vdd oscout oscin vpp pb0/vref/ain0 pb1/ain1 pb2/ain2 pb3/ain3 pb4/ain4 pb5/ain5 pb6/ain6 pb7ain7 pc0/sck pc1/mosi pa5/tclk/tx vdd oscout oscin vpp pb0/vref/ain0 pb1/ain1 pb2/ain2 pb3/ain3 pb4/ain4 pb5/ain5 pb6/ain6 pb7/ain7 pc0/sck pc1/mosi vss reset pa0/scl pa1/sda pa2/t1out pa3/rx pa4/tstrt pa5/tclk/tx pa6/t0out pa7/int pc5/tres pc4/tx pc3/ss pc2/miso 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 so28 15 16 n.c. n.c. 30 29 32 31 vddio vssio a b c d e f 123456 pa5 tx tclk n.c. vpp vddio vss reset pa0/scl n.c. pb0 vref ain0 oscin vdd vssio n.c. pb1 ain1 pb2 ain2 pb4 ain4 oscout n.c. pa2 t1out pb3 ain3 pb5 ain5 pc3 ss pa1 sda pa3 rx pa4 tstrt n.c. pb7 ain7 pc1 mosi pc4 tx pa6 t0out pb6 ain6 n.c. pc0 sck pc2 miso pc5 tres pa7 int
st52f510/f513/f514 13/137 see section output driving current in electrichal characteristics chapter for class explanation table 1.2 st52f510/f513/f514 sdip32 pin list sdip32 name class programming phase working phase 1 vdd digital power supply digital power supply 2 vddio digital power supply digital i/o ports power supply 3 oscout oscillator output 4 oscin oscillator input 5 vpp programming mode selector programming mode selector 6 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input 7 pb1/ain1 a digital i/o, analog input 8 pb2/ain2 a digital i/o, analog input 9 pb3/ain3 a digital i/o, analog input 10 pb4/ain4 a digital i/o, analog input 11 pb5/ain5 a digital i/o, analog input 12 pb6/ain6 a digital i/o, analog input 13 pb7/ain7 a digital i/o, analog input 14 pc0/sck a digital i/o, spi serial clock 15 pc1/mosi a digital i/o, spi master out slave in 16 n.c not connected 17 n.c not connected 18 pc2/miso a digital i/o, spi master in slave out 19 pc3/ss a digital i/o, spi slave select 20 pc4/tx a digital i/o, sci transmission 21 pc5/tres a digital i/o, timer/pwm 0 reset 22 pa7/int a digital i/o, non maskable interrupt 23 pa6/t0out a digital i/o, timer/pwm 0 output 24 pa5/tclk/tx a digital i/o, timer/pwm 0 clock 25 pa4/tstrt a digital i/o, timer/pwm 0 start/stop 26 pa3/rx a digital i/o, sci reception 27 pa2/t1out a digital i/o, timer/pwm 1 output 28 pa1/sda b serial data i/o digital i/o, i 2 c serial data i/o 29 pa0/scl b serial clock digital i/o, i 2 c serial clock 30 reset general reset general reset 31 vssio digital ground digital i/o ports ground 32 vss digital ground digital ground
st52f510/f513/f514 14/137 table 1.3 st52f510/f513/f514 so28 pin list so28 name class programming phase working phase 1 vdd digital power supply digital power supply 2 oscout oscillator output 3 oscin oscillator input 4 vpp programming mode selector programming mode selector 5 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input 6 pb1/ain1 a digital i/o, analog input 7 pb2/ain2 a digital i/o, analog input 8 pb3/ain3 a digital i/o, analog input 9 pb4/ain4 a digital i/o, analog input 10 pb5/ain5 a digital i/o, analog input 11 pb6/ain6 b digital i/o, analog input 12 pb7/ain7 a digital i/o, analog input 13 pc0/sck a digital i/o, spi serial clock 14 pc1/mosi a digital i/o, spi master out slave in 15 pc2/miso a digital i/o, spi master in slave out 16 pc3/ss a digital i/o, spi slave select 17 pc4/tx a digital i/o, sci transmission 18 pc5/tres a digital i/o, timer/pwm 0 reset 19 pa7/int a digital i/o, non maskable interrupt 20 pa6/t0out a digital i/o, timer/pwm 0 output 21 pa5/tclk/tx a digital i/o, timer/pwm 0 clock 22 pa4/tstrt a digital i/o, timer/pwm 0 start/stop 23 pa3/rx a digital i/o, sci reception 24 pa2/t1out a digital i/o, timer/pwm 1 output 25 pa1/sda b serial data i/o digital i/o, i 2 c serial data i/o 26 pa0/scl b serial clock digital i/o, i 2 c serial clock 27 reset general reset general reset 28 vss digital ground digital ground
st52f510/f513/f514 15/137 table 1.4 st52f510/f513/f514 so16 pin list so16 name class programming phase working phase 1 vdd digital power supply digital power supply 2 oscout oscillator output 3 oscin oscillator input 4 vpp programming mode selector programming mode selector 5 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input 6 pb1/ain1 a digital i/o, analog input 7 pa7/int b digital i/o, non maskable interrupt 8 pa6/t0out b digital i/o, timer/pwm 0 output 9 pa5/tclk/tx b digital i/o, timer/pwm 0 clock, sci transmission 10 pa4/tstrt b digital i/o, timer/pwm 0 start/stop 11 pa3/rx a digital i/o, sci reception 12 pa2/t1out a digital i/o, timer/pwm 1 output 13 pa1/sda a serial data i/o digital i/o, i 2 c serial data i/o 14 pa0/scl a serial clock digital i/o, i 2 c serial clock 15 reset general reset general reset 16 vss digital ground digital ground
st52f510/f513/f514 16/137 table 1.5 st52f510/f513/f514 lfbga 6x6 pin list lfbga36 name class programming phase working phase a1 n.c. not connected a2 vpp programming mode selector programming mode selector a3 vddio digital power supply digital i/o ports power supply a4 vss digital ground digital ground a5 reset general reset general reset a6 pa0/scl b serial clock digital i/o, i 2 c serial clock b1 n.c. not connected b2 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input b3 oscin oscillator input b4 vdd digital power supply digital power supply b5 vssio digital ground digital i/o ports ground b6 n.c. not connected c1 pb1/ain1 a digital i/o, analog input c2 pb2/ain2 a digital i/o, analog input c3 pb4/ain4 a digital i/o, analog input c4 oscout oscillator output c5 n.c. not connected c6 pa2/t1out a digital i/o, timer/pwm 1 output d1 pb3/ain3 a digital i/o, analog input d2 pb5/ain5 a digital i/o, analog input d3 pc3/ss a digital i/o, spi slave select d4 pa1/sda a serial data i/o digital i/o, i 2 c serial data i/o d5 pa3/rx a digital i/o, sci reception d6 pa4/tstrt a digital i/o, timer/pwm 0 start/stop e1 n.c. not connected e2 pb7/ain7 a digital i/o, analog input e3 pc1/mosi a digital i/o, spi master out slave in e4 pc4/tx a digital i/o, sci transmission e5 pa5/tclk/tx a digital i/o, timer/pwm 0 clock, sci transmission e6 pa6/t0out b digital i/o, timer/pwm 0 output f1 n.c. not connected f2 pb6/ain6 a digital i/o, analog input f3 pc0/sck a digital i/o, spi serial clock f4 pc2/miso a digital i/o, spi master in slave out f5 pc5/tres a digital i/o, timer/pwm 0 reset f6 pa7/int a digital i/o, non maskable interrupt
st52f510/f513/f514 17/137 table 1.6 st52f510/f513/f514 so20 pin list so20 name class programming phase working phase 1 vdd digital power supply digital power supply 2 oscout oscillator output 3 oscin oscillator input 4 vpp programming mode selector programming mode selector 5 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input 6 pb1/ain1 a digital i/o, analog input 7 pb2/ain2 a digital i/o, analog input 8 pb3/ain3 a digital i/o, analog input 9 pb4/ain4 b digital i/o, analog input 10 pb5/ain5 b digital i/o, analog input 11 pa7/int b digital i/o, non maskable interrupt 12 pa6/t0out b digital i/o, timer/pwm 0 output 13 pa5/tclk/tx a digital i/o, timer/pwm 0 clock, sci transmission 14 pa4/tstrt a digital i/o, timer/pwm 0 start/stop 15 pa3/rx a digital i/o, sci reception 16 pa2/t1out a digital i/o, timer/pwm 1 output 17 pa1/sda a serial data i/o digital i/o, i 2 c serial data i/o 18 pa0/scl a serial clock digital i/o, i 2 c serial clock 19 reset general reset general reset 20 vss digital ground digital ground
st52f510/f513/f514 18/137 table 1.7 st52f510/f513/f514 dip20 pin list dip20 name class programming phase working phase 1 vdd digital power supply digital power supply 2 oscout oscillator output 3 oscin oscillator input 4 vpp programming mode selector programming mode selector 5 pb0/vref/ain0 a digital i/o, a/d voltage reference, analog input 6 pb1/ain1 a digital i/o, analog input 7 pb2/ain2 b digital i/o, analog input 8 pb3/ain3 b digital i/o, analog input 9 pb4/ain4 b digital i/o, analog input 10 pb5/ain5 b digital i/o, analog input 11 pa7/int b digital i/o, non maskable interrupt 12 pa6/t0out b digital i/o, timer/pwm 0 output 13 pa5/tclk/tx b digital i/o, timer/pwm 0 clock, sci transmission 14 pa4/tstrt b digital i/o, timer/pwm 0 start/stop 15 pa3/rx a digital i/o, sci reception 16 pa2/t1out a digital i/o, timer/pwm 1 output 17 pa1/sda b serial data i/o digital i/o, i 2 c serial data i/o 18 pa0/scl b serial clock digital i/o, i 2 c serial clock 19 reset general reset general reset 20 vss digital ground digital ground
st52f510/f513/f514 19/137 1.3 pin description st52f510/f513/f514 pins can be set in digital input mode, digital output mode, interrupt mode or in alternate functions. pin configuration is achieved by means of the configuration registers. the functions of the st52f510/f513/f514 pins are described below: v dd. main power supply voltage. v ddio. i/o ports power supply voltage. it is reccomended to connect this pin with a supply voltage de-coupled with v dd in order to improve the immunity from the noise generated by the i/o switching. v ss . digital circuit ground. v ssio . i/o ports ground. see v ddio v pp . programming/working mode selector. during the programming phase v pp must be set to v dd . in working phase v pp must be equal to v ss . oscin and oscout. these pins are internally connected to the on-chip oscillator circuit. a quartz crystal or a ceramic resonator can be connected between these two pins in order to allow correct use of st52f510/f513/f514 with various stability/ cost trade-offs. an external clock signal can be applied to oscin: in this case oscout can be floating. without any connection, the device can work with its internal clock generator (10 mhz) reset . this signal is used to reset the st52f510/ f513/f514 and re-initialize the registers and control signals. it is also used when switching from the programming mode to working mode and vice versa. pa0-pa7, pb0-pb7,pc0-pc5 . these lines are organized as i/o ports. each pin can be configured as an input, output (with pull-up, push-pull, weak- pull-up, open-drain, high-impedance), or as an interrupt source. vref, ain0-ain7 . these pins are used to input the analog signals into the a/d converter. an analog multiplexer is available to switch these inputs to the a/d converter. the pin vref is used to input an external a/d reference voltage. t0out, t1out . these pins output the signals generated by the pwm/timer 0 and pwm/timer 1 peripheral. tres , tstrt, tclk . these pins are related to the pwm/timer 0 peripheral and are used for input capture and event counting. the tres pin is used to set/reset the timer; the tstrt pin is used to start/stop the counter. the timer can be driven by the internal clock or by an external signal connected to the tclk pin. int . this pin is used as input for the non-maskable (top level) interrupt. the interrupt signal is detected only if the pin is configured in alternate function. scl, sda . these pin are used respectively as serial clock and serial data i/o in i 2 c peripheral protocol. they are used also in programming mode to receive and transmit data. tx, rx. serial data output of sci transmitter block (tx) and serial data input of the sci receiver block (rx). sck, miso, mosi, ss . these pins are used by the serial peripheral interface (spi) peripheral. sck is the serial clock line. miso (master in slave out) and mosi (master out slave in) are the serial data lines, which work in input or in output depending on if the device is working in slave or master mode. the ss pin allows the selection of the device master/slave mode.
st52f510/f513/f514 20/137 2 internal architecture st52f510/f513/f514 ? s architecture is register file based and is composed of the following blocks and peripherals: control unit (cu) data processing unit (dpu) decision processor (dp) alu memory interface up to 256 bytes register file program/data memory data eeprom interrupts controller clock oscillator plvd and por digital i/o ports analog multiplexer and a/d converter timer/pwms i 2 c spi sci figure 2.1 cu block diagram 2.1 control unit and data processing unit the control unit (cu) decodes the instructions stored in the program memory and generates the appropriate control signals. the main parts of the cu are illustrated in figure 2.1 . the five different parts of the cu manage loading, logic/arithmetic, jump, control and the fuzzy instruction set. the block called ? collector ? manages the signals deriving from the different parts of the cu. the collector defines the signals for the data processing unit (dpu) and decision processor (dp), as well as for the different peripherals of the icu. the block called ? arbiter ? manages the different parts of the cu, so that only one part of the system is activated during working mode. the cu structure is extremely flexible and was designed with the purpose of easily adapting the core of the microcontroller to market needs. new instruction sets or new peripherals can easily be included without changing the structure of the microcontroller, maintaining code compatibility. a set of 107 different instructions is available. each instruction requires a number of clock pulses to be performed that depends on the complexity of the instruction itself. the clock pulses to execute the instructions are driven directly by the masterclock, which has the same frequency of the oscillator signal supplied. loading instruction set logic arithmetic instruction set jump instruction set control instruction set decision processor instruction set c o l l e c t o r control signals a r b i t e r microcode clock master
st52f510/f513/f514 21/137 figure 2.2 data processing unit (dpu) the dpu receives, stores and sends the instructions deriving from the program/data memory, register file or from the peripherals. it is controlled by the cu on the basis of the decoded instruction. the fuzzy registers store the partial results of the fuzzy computation. the accumulator register is used by the alu and is not accessible directly: the instructions used by the alu can address all the register file locations as operands, allowing a more compact code and a faster execution. the following addressing modes are available: inherent, immediate, direct, indirect, bit direct. 2.1.1 program counter. the program counter (pc) is a 16-bit register that contains the address of the next memory location to be processed by the core. this memory location may be both an instruction or data address. the program counter ? s 16-bit length allows the direct addressing of a maximum of 64 kbytes in the program/data memory space. the pc can be changed in the following ways: jp (jump) pc = jump address interrupt pc = interrupt vector reti pc = pop (stack) ret pc = pop (stack) call pc = subroutines address reset pc = reset vector normal instruction pc = pc + instr. lenght 2.1.2 flags. the st five core includes different sets of flags that correspond to 2 different modes: normal mode and interrupt mode. each set of flags consist of a carry flag (c), zero flag (z) and sign flag (s). each set is stacked: one set of flags is used during normal operation and other sets are used during each level of interrupt. formally, the user has to manage only one set of flags: c, z and s since the flag stack operation is performed automatically. program counter register file 256 bytes register file address accumulator decision registers alu flags reg. memory address peripherals control unit program memory input registers peripherals interrupts unit processor
st52f510/f513/f514 22/137 each interrupt level has its own set of flags, which is saved in the flag stack during interrupt servicing. these flags are restored from the flag stack automatically when a reti instruction is executed. if the icu was in normal mode before an interrupt, after the reti instruction is executed, the normal flags are restored. note: a subroutine call is a normal mode execution. for this reason a ret instruction, consequent to a call instruction, doesn?t affect the normal mode set of flags. flags are not cleared during context switching and remain in the state they were in at the exit of the last interrupt routine switching. the carry flag is set when an overflow occurs during arithmetic operations, otherwise it is cleared. the sign flag is set when an underflow occurs during arithmetic operations, otherwise it is cleared. the flags, related to the current context, can be checked by reading the flags input register 38 (026h). figure 2.3 multiplication 2.2 arithmetic logic unit the 8-bit arithmetic logic unit (alu) performs arithmetic calculations and logic instructions such as: sum, subtraction, bitwise and, or, xor, bit set and reset, bit test and branch, right/left shift and rotate (see chapter 9 instruction set for further details). in addition, the alu of st52f510/f513/f514 can perform multiplication (mult) and division (div). multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values); the division instruction addresses the msb of the dividend (the lsb is stored in the next address): the result and remainder are stored in these source addresses (see figure 2.3 and figure 2.4 ). in order to manage signed type values, the alu also performs addition and subtraction with offset (addo and subo). these instructions respectively subtract and add 128 to the overall result, in order to manage values logically in the range between -128,127. figure 2.4 division ram 000h 001h 002h i j+1 j-1 j 0ffh 0fdh 0feh reg. j reg. i lsb msb x 16 bit ram i j+1 j-1 j reg. j reg. j+1 remainder quotient reg. i : i-1 i+1 000h 001h 002h 0ffh 0fdh 0feh
st52f510/f513/f514 23/137 2.3 register description flags register (flag) input register 38 (026h) read only reset value: 0000 0000 (00h) bit 7-3: not used bit 2: z zero flag bit 1: s sign flag bit 0: c carry flag 70 -----zsc
st52f510/f513/f514 24/137 3 addressing spaces st52f510/f513 has six separate addressing spaces: register file program/data memory and stacks input registers output registers configuration registers fuzzy registers note: stack is in the same address space of program memory. each space is addressed by a load type instruction that indicates the source and the destination space in the mnemonic code (see figure 3.1 ). 3.1 memory interface the read/write operation in the space addresses are managed by the memory interface, which can recognize the type of memory addressed and set the appropriate access time and mode. in addition, the memory interface manages the in application programming (iap) functions in flash devices like writing cycle and memory write protection. figure 3.1 addressing spaces 3.2 register file the register file consists of 256 general purpose 8-bit ram locations called ? registers ? in order to recall the functionality. the register file exchanges data with all the other addressing spaces and is used by the alu to perform all the arithmetic and logic instructions. these instructions have any register file address as operands. data can be moved from one location to another by using the ldrr instruction; see further ahead for information on the instruction used to move data between the register file and the other addressing spaces. 3.3 program/data memory the program/data memory consists of both non- volatile memory (flash, eeprom) and ram memory benches. non-volatile memory (nvm) is mainly used to store the user program and can also be used to store permanent data (constant, look-up tables). each ram bench consists of 256 locations used to store run-time user data. at least one bench is present in the devices. ram benches are also used to implement both system and user stacks. nvm & ram locations can be accessed by means of the lder and ldre instructions. cu dpu alu peripheral block register file input registers non volatile memory ram banks and stacks program/data memory stfive core on chip peripherals output registers configuration registers peripheral block peripheral block lder ldre ldri ldce ldcr decision processor registers ldfr ldpe ldpr ldcnf program counter pgsetr getpg
st52f510/f513/f514 25/137 nvm is always located beginning after the first locations of the addressing space. ram banks are always located after nvm. nvm is organized in accordance to the following blocks (see figure 3.2 ): reset vector block (from address 0 to 2) contains an absolute jump instruction to the first user program instruction. the assembler tool automatically fills these locations with correct data. interrupt vectors block (from location 3 up to 32) contains the interrupt vectors. each address is composed of three bytes (the jump opcode and the 16 bit address). interrupt vectors are set by using irq pseudo-instruction (see the programming manual). figure 3.2 program/data memory organization mbfs setting block (just after the interrupt vectors) contains the coordinates of the vertexes of every mbf defined in the program. the last address that can be assigned to this block is 1023. this area is dynamically assigned according to the size of the fuzzy routines. the memory area that remains unused, if any, is assigned to the program instructions block. the program instructions block (just after the last mbf data through the last nvm address) contains the instruction of the user program and the permanent data. option bytes block (from location 3000h to 307fh) is the addressing space reserved for the option bytes. in st52f510/f513, only the location from 3000h to 3007h are used.
st52f510/f513/f514 26/137 flash and eeprom are programmed electrically just applying the supply voltage and they are also erased electrically; this feature allows the user to easily reprogram the memory without taking the device off from the board (in situ programming isp). data and commands are transmitted through the i 2 c serial communication protocol. data can also be written run-time with the in application programming (iap) nvm can be locked by the user during the programming phase, in order to prevent external operation such as reading the program code and assuring protection of user intellectual property. flash and eeprom pages can be protected by unintentional writings. the operations that can be performed on the nvm during the programming phase, isp and iap are described in detail in the section 4 . figure 3.3 system and user stack 3.4 system and user stacks the system and user stacks are located in the program/data memory in the ram benches. system stacks are used to push the program counter (pc) after an interrupt request or a subroutine call. after a ret (return from a subroutine) or a reti (return from an interrupt) the pc that is saved is popped from the stack and restored. after an interrupt request, the flags are also saved in a reserved stack inside the core, so each interrupt has its own flags. the system stack is located in the last ram bench starting from the last address (20ffh) inside the bench page. the system stack pointer (ssp) can be read and modified by the user. for each level of stack 2 bytes of the ram are used. the ssp points to the first currently available stack position. when a subroutine call or interrupt request occurs, the content of the pc is stored in a couple of locations pointed to by the ssp that is decreased by 2. 20ffh 2000h 2001h 20feh register file configuration registers user stack top msb user stack top lsb program counter ram bench system stack pointer user stack pointer user data page number location adress irq reti pop x push x register x lsb msb system stack system stack system stack system stack level 1 level 2 level 3 level 4 user stack level 1 user stack level 2 user stack level 3 user stack level 4
st52f510/f513/f514 27/137 when a return occurs (ret or reti instruction), the ssp is increased by 2 and the data stored in the pointed locations couple is restored back into the pc. the current ssp can be read and write in the couple of configuration registers 44 02ch (msb: page number, always 32 020h) and 45 02dh (lsb: location address) (see figure 3.3 ). in st52f510/ f513 the user can only consider the lsb because the msb is always the same. the user stack is used to store user data and is located beginning from a ram bench location set by the user (ustp) by writing the couple of configuration registers 5 005h (msb: page number) and 6 006h (lsb: location address) (see figure 3.3 ). register 5, which is the page number, must always be set to a value between 32 (020h) and 255 (0ffh): values higher than 32 always address ram on page 32. note: in st52f510/f513 msb doesn ? t have to be set or read because the ram is only 256 bytes. the lsb of the user stack is equal to 0 at reset. the lsb of the system stack is equal to 255 at reset. this feature allows a flexible use of the user stack in terms of dimension and to avoid overlaps. the user stack pointer (usp) points to the first currently available stack location. when the user stores a byte value contained in the register file by using the push instruction, the value is stored in the position pointed to by the usp that is increased (the user stack order is opposite to the system stack one). when the user takes a value from the user stack with the pop instruction, the usp is decreased and the value pointed to is copied in the specified register file location. by writing the ustp, the new address is automatically written in the usp. the current usp can be read from the input registers 11 0bh (msb: page number, always 32 020h) and 12 0ch (lsb: location address) (see figure 3.3 ). in st52f510/f513 the user can only consider the lsb because the msb is always the same. note: the user must pay close attention to avoid overlapping user and stacks data. the user stack top location and the system stack pointer should be configured with care in order to have enough space between the two stacks. 3.5 input registers the st52f510/f513 input registers bench consists of a file of 8-bit registers containing data or the status of the peripherals. for example, the input registers contain data converted by the adc, ports, serial communication peripherals, timers, etc. the input registers can be accessed by using the ldri instruction that loads the specified register file address with the contents of the specified input register. see the programming manual for further details on this instruction. the input registers are read-only registers. in order to simplify the concept, a mnemonic name is assigned to each register. the same name is used in visual five development tools. the list of the input registers is shown in table 3.1 . 3.6 output registers the st52f510/f513 output registers bench consists of a file of 8-bit registers containing data sent to the peripherals and the i/o ports (for example: timer counters, data to be transmitted by the serial communication peripherals, data to be sent to the port pins in output, etc.). the registers are located inside the peripherals and ports, which allow flexibility and modularity in the design of new family devices. the output registers are write only. in order to access the configuration register the user can use the following instructions: ldpi: loads the immediate value in the specified output register. ldpr: loads the contents of the specified register file location into the output register specified. this instruction allows computed data to be sent to peripherals and ports. ldpe direct: loads the contents of the specified program/data memory location into the output register specified. this instruction allows data to be sent to peripherals and ports from a table. ldpe indirect: loads the contents of the program/data memory location whose address is contained in the specified register file location into the output register specified. this instruction allows data to be sent to peripherals and ports from a table pointed to by a register. see the programming manual for further details about these instructions. in order to simplify the concept, a mnemonic name is assigned to each register. the same name is used in visual five development tools. the list of the output registers is shown in table 3.2 .
st52f510/f513/f514 28/137 3.7 configuration registers & option bytes the st52f510/f513 configuration registers bench consists of a file of 8-bit registers that allows the configuration of all the icu blocks. the registers are located inside the block they configure in order to obtain greater flexibility and modularity in the design of new family devices. in the configuration registers, each bit has a particular use, so the logic level of each of them must be considered. some special configuration data, that needs to be load at the start-up and not further changed, are stored in option bytes. these are loaded only during the device programming phase. see table 3.3 and section 4 for a detailed description of the option bytes. the configuration registers are readable and writable; the addresses refer to the same register both in read and in write. in order to access the configuration register the user can work in several modes by utilizing the following instructions: ldci: loads the immediate value in the configuration register specified and is the most commonly used to write configuration data. ldcr: loads the configuration register specified with the contents of the specified register file location, allowing a parametric configuration. ldce: loads the configuration register specified with the contents of the specified program/data memory location, allowing the configuration data to be taken from a table. ldcnf: loads the register file location specified with the contents of the configuration register indicated, allowing for the inspection of the configuration of the device (permitting safe run-time modifications). in order to simplify the concept, a mnemonic name is assigned to each register. the same name is used in visual five development tools. the list of the configuration registers is shown in table 3.4 . 3.8 fuzzy registers the decision processor for fuzzy computation is accessed by means of 8 dedicated registers. these registers are used to load values in input to the decision processor. the values are loaded in the fuzzy register by mean of the ldfr instruction. this instruction set the specified fuzzy register (addresses from 0 to 7) with the value stored in the specified address of the register file. see chapter 8 fuzzy computation (dp) for further informations.
st52f510/f513/f514 29/137 table 3.1 input registers mnemonic description address port_a_in port a data input register 0 00h port_b_in port b data input register 1 01h port_c_in port c data input register 2 02h - not used 3 03h - not used 4 04h spi_in serial peripheral interface data input register 5 05h i2c_in i 2 c interface data input register 606h i2c_sr1 i 2 c interface status register 1 707h i2c_sr2 i 2 c interface status register 2 808h - not used 9 09h - not used 10 0ah usp_h user stack pointer (msb) 11 0bh usp_l user stack pointer (lsb) 12 0ch - not used 13-20 0dh- 014h pwm0_count_in_h pwm/timer 0 counter input register (msb) 21 015h pwm0_count_in_l pwm/timer 0 counter input register (lsb) 22 016h pwm0_status pwm/timer 0 status register 23 017h pwm0_capture_h pwm/timer 0 capture register (msb) 24 018h pwm0_capture_l pwm/timer 0 capture register (lsb) 25 019h pwm1_count_in_h pwm/timer 1 counter input register (msb) 26 01ah pwm1_count_in_l pwm/timer 1 counter input register (lsb) 27 01bh pwm1_status pwm/timer 1 status register 28 01ch pwm1_capture_h pwm/timer 1 capture register (msb) 29 01dh pwm1_capture_l pwm/timer 1 capture register (lsb) 30 01eh - not used 31-35 01fh- 023h sci_in serial communication interface rx data input register 36 024h sci_status serial communication interface status register 37 025h flags flag register 38 026h ad_ovf 10-bit a/d converter overflow register 39 027h iap_sr in application programming status register 40 028h
st52f510/f513/f514 30/137 chan0_h 10-bit a/d converter channel 0 data input register (msb) 41 029h chan0_l 10-bit a/d converter channel 0 data input register (lsb) 42 02ah chan1_h 10-bit a/d converter channel 1 data input register (msb) 43 02bh chan1_l 10-bit a/d converter channel 1 data input register (lsb) 44 02ch chan2_h 10-bit a/d converter channel 2 data input register (msb) 45 02dh chan2_l 10-bit a/d converter channel 2 data input register (lsb) 46 02eh chan3_h 10-bit a/d converter channel 3 data input register (msb) 47 02fh chan3_l 10-bit a/d converter channel 3 data input register (lsb) 48 030h chan4_h 10-bit a/d converter channel 4 data input register (msb) 49 031h chan4_l 10-bit a/d converter channel 4 data input register (lsb) 50 032h chan5_h 10-bit a/d converter channel 5 data input register (msb) 51 033h chan5_l 10-bit a/d converter channel 5 data input register (lsb) 52 034h chan6_h 10-bit a/d converter channel 6 data input register (msb) 53 035h chan6_l 10-bit a/d converter channel 6 data input register (lsb) 54 036h chan7_h 10-bit a/d converter channel 7 data input register (msb) 55 037h chan7_l 10-bit a/d converter channel 7 data input register (lsb) 56 038h table 3.1 input registers mnemonic description address
st52f510/f513/f514 31/137 table 3.2 output registers mnemonic description address port_a_out port a data output register 0 00h port_b_out port b data output register 1 01h port_c_out port c data output register 2 02h - not used 3 03h - not used 4 04h spi_out serial peripheral interface data output register 5 05h i2c_out i 2 c interface data output register 606h pwm0_count_out_h pwm/timer 0 counter output register (msb) 7 07h pwm0_count_out_l pwm/timer 0 counter output register (lsb) 8 08h pwm0_reload_h pwm/timer 0 reload register (msb) 9 09h pwm0_reload_l pwm/timer 0 reload register (lsb) 10 0ah pwm1_count_out_h pwm/timer 1 counter output register (msb) 11 0bh pwm1_count_out_l pwm/timer 1 counter output register (lsb) 12 0ch pwm1_reload_h pwm/timer 1 reload register (msb) 13 0dh pwm1_reload_l pwm/timer 1 reload register (lsb) 14 0eh sci_out serial communication interface tx data output register 23 017h table 3.3 option bytes mnemonic description address osc_cr oscillator control register 0 00h clk_set clock parameters 1 01h osc_set oscillator set-up 2 02h pldv_cr programmable low voltage detector control register 3 03h wdt_en hw/sw watchdog selector 4 04h pg_lock first page write protected 5 05h pg_unlock first page not write protected 6 06h wakeup wake up from halt time 7 07h
st52f510/f513/f514 32/137 table 3.4 configuration registers mnemonic description address int_mask interrupt mask register 0 00h int_pol interrupts polarity 1 01h int_prl_l interrupt priority register (lower priority) 2 02h int_prl_m interrupt priority register (medium priority) 3 03h int_prl_h interrupt priority register (higher priority) 4 04h ustp_h user stack top pointer (msb) 5 05h ustp_l user stack top pointer (lsb) 6 06h wdt_cr watchdog configuration register 7 07h ad_cr1 10-bit a/d converter control register 1 8 08h pwm0_cr1 pwm/timer 0 configuration register 1 9 09h pwm0_cr2 pwm/timer 0 configuration register 2 10 0ah pwm0_cr3 pwm/timer 0 configuration register 3 11 0bh pwm1_cr1 pwm/timer 1 configuration register 1 12 0ch pwm1_cr2 pwm/timer 1 configuration register 2 13 0dh - not used 14 0eh - not used 15 0fh i2c_cr i 2 c interface control register 16 010h i2c_ccr i 2 c interface clock control register 17 011h i2c_oar1 i 2 c interface own address register 1 18 012h i2c_oar2 i 2 c interface own address register 2 19 013h spi_cr serial peripheral interface control register 20 014h spi_status_cr serial peripheral interface control-status register 21 015h sci_cr1 serial communication interface control register 1 22 016h sci_cr2 serial communication interface control register 2 23 017h port_a_pullup port a pull up enable/disable register 24 018h port_a_or port a option register 25 019h
st52f510/f513/f514 33/137 port_a_ddr port a data direction register 26 01ah port_a_af port a alternate function selection register 27 01bh port_b_pullup port b pull up enable/disable register 28 01ch port_b_or port b option register 29 01dh port_b_ddr port b data direction register 30 01eh port_b_af port b alternate function selection register 31 01fh port_c_pullup port c pull up enable/disable register 32 020h port_c_or port c option register 33 021h port_c_ddr port c data direction register 34 022h port_c_af port c alternate function selection register 35 023h - not used 36-42 024h- 02ah sci_cr3 serial communication interface control register 3 43 02bh ssp_h system stack pointer (msb) 44 02ch ssp_l system stack pointer (lsb) 45 02dh cpu_clk cpu clock prescaler 46 02eh ad_cr2 10-bit a/d converter control register 2 47 02fh table 3.4 configuration registers mnemonic description address
st52f510/f513/f514 34/137 4 memory programming st52f510/f513 provides an on-chip user programmable non-volatile memory, which allows fast and reliable storage of user data. program/data memory addressing space is composed by a single voltage flash memory and a ram memory bench. the st52f513/514 devices also have a data eeprom bench to store permanent data with long term retention and a high number of write/erase cycles. all the program data memory addresses can execute code, including ram and eeprom benches. the memory is programmed by setting the v pp pin equal to v dd . data and commands are transmitted through the i 2 c serial communication protocol. the same procedure is used to perform ? in-situ ? the programming of the device after it is mounted in the user system. data can also be written in run- time with the in-application programming (iap) instructions. the memory can be locked by the user during the programming phase, in order to prevent external operation such as reading the program code and assuring protection of user intellectual property. flash and eeprom pages can be protected by unintentional writings. remark: the memory contents are protected by the error correction code (ecc) algorithm that uses a 4-bit redundancy to correct one bit errors. 4.1 program/data memory organization the program/data memory is organized as described in section 3.3 . the various sales types have different amounts of each type of memory. table 4.1 describes the memory benches amount and page allocation for each sales type. the addressing spaces are organized in pages of 256 bytes. each page is composed by blocks of 32 bytes. memory programming is performed one block at a time in order to speed-up the programming time (about 2.5 ms per block). the whole location address is composed as follows: 15 87 54 0 page address block address address inside the block table 4.1 sales type memory organization device flash memory ram memory eeprom memory amount pages amount page amount page(s) st52f510c2p6 4096 bytes 0 to 15 256 bytes 32 - - st52f510c3p6 8192 bytes 0 to 31 256 bytes 32 - - st52f513c2p6 3840 bytes 0 to 14 256 bytes 32 256 bytes 15 st52f513c3p6 7936 bytes 0 to 30 256 bytes 32 256 bytes 31 st52f514c1p6 4096 bytes 0 to 15 256 bytes 32 1024 bytes 16-19 st52f514c3p6 4096 bytes 0 to 15 256 bytes 32 4096 bytes 16-31 legend: c: y=16 pins, f=20 pins, g=28 pins, k=32/34 pin p: b=dip, m=so, t=tqfp
st52f510/f513/f514 35/137 4.2 memory programming the programming procedure writes the user program and data into the flash memory, eeprom and option bytes. the programming procedures are entered by setting the v pp pin equal to v dd and releasing the reset signal. the following pins are used in programming mode: v pp used to switch to programming mode v dd device supply v ss device ground reset device reset scl i 2 c serial clock sda i 2 c serial data during the device programming, the internal clock is used, so the oscin and oscout pins don ? t have to be considered. remark: the option bytes must be always programmed, otherwise these bytes will be loaded with unpredictable values, determining unpredictable device configuration. 4.2.1 programming mode start. the following sequence starts the programming mode: 1. v pp is set to v dd 2. the device is reset (reset=v ss ) 3. the reset is released (reset=v dd ) 4. the internal oscillator starts at 10 mhz 5. the memory is turned on 6. the i 2 c interface and ports are initialized 7. the i 2 c interface is configured to work as slave, receiver, 7-bit address and waits for data 8. the start signal is sent to the chip followed by the slave address 1010000 and the direction bit set to 0 (the addressed slave waits for da- ta). the device sends the acknowledge 9. the programming mode code 00000000 is sent and acknowledged 10. a command code is sent to the device 11. the procedure related to the command is ex- ecuted table 4.2 programming mode commands command code data in data out erase description blockwrite 00000001 32 - yes write the currently addressed block with the 32 bytes following the command. the block locations are erased before being written. bytewrite 00000010 2 - yes write the byte addressed by the next data sent in the currently addressed page. blockerase 00000011 1 yes erase the block addressed by 3 msb of the next data sent and inside the currently addressed page. byteerase 00000100 1 yes erase the byte addressed by the next data sent and inside the currently addressed page. byteread 00000101 1 1 - read the byte addressed by the next data sent and inside the current page. the read data is sent by the device after the re-send of the slave address with the r/w bit changed. the current memory absolute address is post-incremented. globalerase 00001001 - - yes all the memory is erased. fastblockwrite 00001011 32 - no write the currently addressed block with the 32 bytes following the command. the block locations aren ? t erased. setpage 00001100 1 - - the currently addressed page is set with the next data sent. readdata 00001101 - 1 - read the memory location currently addressed. the read data is sent by the device after the command is acknowledged. the current memory absolute address is post-incremented. incblock 00001111 - - - the current block address is incremented modulo 8 (address 0 follows after address 7 and the page is post- incremented) readstatus 00010011 - 1 - this command is followed by a status data byte. mostly used in error condition and to check if the device is locked
st52f510/f513/f514 36/137 figure 4.1 commands and data communication sequences the generic procedure of commands execution, with the data communication in both directions is displayed in figure 4.1 . remark: the slave address 1010000 must be sent after a stop (i.e. each time the data direction changes, to specify the r/w bit). for example: if a command to send data to the device has been executed, a command for receiving data must be followed by the slave address and the r/w bit must be set to 1. the programming mode code doesn ? t need to be specified again . warning: after entering the programming mode, the currently pointed address is the page 48, block 3, byte 0 (lock byte). the list of the available commands in programming mode is showed in table 4.2 4.2.2 fast programming procedure. the fastest way to program the device memory is the use of the fastblockwrite command. the following procedure can be used to write the memory with a new program and new data, starting from the first memory location: 1. the programming mode is entered with the sequence described above 2. the memory is erased (all bits are put to 0) with the globalerase command. the device holds the scl line low, releasing it after the command is completed (about 2 ms). this command also unlocks the device if locked. 3. the fastblockwrite command is sent and the device acknowledges it 4. the 32 bytes of data to be written in the first memory block are sent in a sequence. the device acknowledges each of them 5. after the device acknowledges the 32nd byte, it holds the scl line until the parallel writing of the 32 byte is completed (about 2.5 ms) 6. the block pointer is incremented by sending the incblock command 7. the procedure is repeated from point 3 until there is data to be sent to the memory note: the block pointer assumes values between 0 to 7 (there are 8 blocks in a page). when the block pointer is equal to 7, the incblock command puts this pointer to 0 and increments the page pointer. the page pointer, after page writing is completed, does ? t have to be incremented in the procedure above described. 4.2.3 random data writing. a single byte can be written in a specified memory location by using the following procedure: 1. the programming mode is entered with the sequence described in section 4.2.1 2. the setpage command is sent, followed by the page number where the data should be written 3. the bytewrite command is sent followed by two bytes 4. the first bytes that follows the bytewrite com- mand is the address inside the pointed page where the data must be written. 5. the second byte is the data to be written 6. the device held the scl line low until the data is not stored in the memory (about 4.5 ms: 2 ms for erasing and 2.5 for writing) programming mode start sequence execution of commands for writing data: execution of commands for reading data: s=start, p=stop, a=acknowledge, na=non-acknowledge from slave to master from master to slave s 1010000 0 a 00000000 a command a data1 a ..... datan ap command adata1 a ..... datan a command adata1 a ..... datan ap command aaddress a p s 1010000 1 a data read na p
st52f510/f513/f514 37/137 a similar procedure can be used to write a single block: 1. the setpage command is sent, followed by the page number where the data should be written 2. the incblock command is sent as many times as the block number inside the page (for ex- ample: to address the block 3 the incblock must be sent 3 times) 3. the block write command is sent followed by the 32 data bytes to be written. 4. after the 32th byte is sent, the device holds the scl line low until all the data are not stored in the memory (about 4.5 ms: 2 ms for erasing and 2.5 for writing: the same time for a single byte) the procedures described previously can be repeated as many time as needed, without exiting from programming mode or re-sending the slave address again. the commands byteerase and blockerase, used instead of bytewrite and blockwrite, erase (put all bit to 0) the specified memory location or block. 4.2.4 option bytes programming. the option byte addresses cannot be accessed with a sequential procedure like the one described in section 4.2.2 . actually, the pointers are automatically incremented up to the last block or address in page 31. a further increment sets all the pointers to 0. the option byte addresses (located at page 48, block 0, addresses 0-7) must be accessed with a direct addressing procedure as the one described in section 4.2.3 . if the fast programming procedure is used, it must be followed by a random block writing procedure to program the option bytes. the other 24 bytes of the block can be written with dummy or user values. the blocks 0, 1, 2 and 3 of page 48 can be used for writing data as well (see section 4.5 ) and for locking the device (see section 4.4 ). figure 4.2 programming procedures fast programming procedure random byte writing procedure random block writing procedure option byte writing procedure s=start, p=stop, a=acknowledge, na=non-acknowledge from slave to master from master to slave s 10100000 a 00000000 a globalerase a fastblockwrite adata0 a ..... ..... data31 a incblock a fastblockwrite a ..... data31 a ..... ..... data31 ap ..... setpage a page address a bytewrite a byte address adata a command ..... ..... setpage a page address a incblock a ..... incblock a blockwrite adata0 a ..... ..... data31 a command ..... ..... setpage a 00110000 a blockwrite a option byte 0 a ..... option byte 7 a ..... ..... dummy 0 a ..... dummy 23 ap
st52f510/f513/f514 38/137 figure 4.3 reading and erasing procedures 4.3 memory verify to verify the memory contents or just to read part of data stored in memory, the byteread and the readdata command can be used. the first instruction needs the specification of the address; the second one allows the sequential reading of consecutive memory locations. since the device is ? slave ? for the i 2 c protocol, after receiving a command for reading, it must be configured as slave transmitter to send the data. in order to do so, the slave address (1010000) must be sent again with the r/w byte set to 1, as stated by the communication protocol. 4.3.1 fast read procedure. the memory can be read sequentially by using the following procedure: 1. the programming mode is entered with the sequence described in section 4.2.1 2. the pointers address the memory location 0 3. the readdata command is sent and the de- vice acknowledges it. 4. the master generates a stop condition fol- lowed by a start condition 5. the slave address with the r/w byte set to 1 (10100001) is sent. the device receives the slave address and acknowledges it. 6. the device sends the data to be read in the serial data line sda. the current absolute ad- dress is post-incremented. 7. the master device doesn ? t send the acknowl- edge and generates a stop condition. 8. to read the next data, the master generates a start condition followed by the slave address with the r/w byte set to 0 (10100000). the device receives the slave address and ac- knowledges it. 9. the sequence restarts from point 3 until there is data to be read. remark: for the same reasons explained in section 4.2.4 the option bytes cannot be read with this procedure: they can be read with a direct addressing procedure as the one explained in the next section. fast reading procedure random byte reading procedure byte erasing procedure block erasing procedure (*) block address is specified by the 3 most significative bits of the whole given address (less significative bits are don ? t care) s=start, p=stop, a=acknowledge, na=non-acknowledge from slave to master from master to slave s 10100000 a 00000000 a readdata a p s 1010000 1 a data read na p ..... ..... s 10100000 a readdata a p s 1010000 1 a data read na p ..... data read na p ..... setpage a page address a byteread a byte address a p s 1010000 1 a ..... ..... data read na p s 1010000 0 a command ..... ..... setpage a page address a byteerase a byte address a command ..... ..... setpage a page address a blockerase a block address (*) a command .....
st52f510/f513/f514 39/137 4.3.2 random data reading. to read a specified memory location, the following procedure should be used: 1. the programming mode is entered with the sequence described in section 4.2.1 2. the setpage command is sent, followed to the page number where the data to be read is located 3. the byteread command is sent, followed by an address inside the page 4. the master generates a stop condition fol- lowed by a start condition 5. the slave address with the r/w byte set to 1 (10100001) is sent. the device receives the slave address and acknowledges it. 6. the device sends the data to be read in the serial data line sda. the address pointer is incremented. 7. the master device doesn ? t send the acknowl- edge and generates a stop condition. 8. to send the next command, the master should generate a start condition followed by the slave address with the r/w byte set to 0 (10100000). figure 4.4 device lock procedure 4.4 memory lock the program/data memory space can be locked to inhibit the reading of contents and protect the intellectual property. to lock the device, the user must set all the bit of the lock byte to ? 1 ? . the lock byte is located on page 48 (030h), block 3, byte 0 inside the block i.e. byte 96 (060h) inside the page. after writing 255 (0ffh) into the lock byte, with the procedure described in the section 4.2.3 , the memory is locked and the only command allowed are the following: ? globalerase : this command, writing ? 0 ? in all the memory, also unlock the device. ? readdata : the only block that can be read is the block 3 in page 48 (030h); this allows the read- ing of the lock byte and the id code locations (see section 4.5 ). ? readstatus : this command allows the detection of an error condition in programming mode op- eration (see section 4.6 ). it can also be used to check if the device is locked. the most significa- tive bit return the lock bit (0=unlocked, 1=locked). remark: the lock byte is checked when entering the programming mode. for this reason after writing the lock byte, all the commands can be carried out until the programming mode is exited. device lock procedure device lock and id code writing procedure device lock reading procedure (*) the most significative bit return the lock bit (0=unlocked, 1=locked) s=start, p=stop, a=acknowledge, na=non-acknowledge from slave to master from master to slave ..... setpage a 00110000 a bytewrite a 01100000 a 11111111 a command ..... ..... setpage a 00110000 a incblock a incblock a incblock a blockwrite a ..... ..... 11111111 a id code 1 aid code 2 a ..... id code 31 a command ..... ..... readstatus a p s 1010000 1 a status byte (*) na p s 1010000 0 a command .....
st52f510/f513/f514 40/137 figure 4.5 error handling procedure when the device is locked, if memory reading is attempted, with the exception of the lock byte and id code block, the device returns no data and an error sequence. if memory writing is attempted in any memory location, the device doesn ? t carry out the command and returns an error sequence. to unlock the device the globalerase command must be executed before any writing or reading command. 4.5 id code block 3 on page 48 (030h) can also be read if the device is locked. the first byte of the block is the lock byte, the following 21 locations (bytes 1-21) are available to the user for writing data, as for example identification codes to distinguish the firmware version loaded in the device. warning: do not perform writing on the last 8 bytes (bytes 22 to 31), because they are reserved. the id code must be written before locking the device: after the device is locked it can only be read. the blocks 0, 1 and 2 on page 48 can be also be used for writing data, but they cannot be accessed when the device is locked. note: the id code cannot be modified if the device is locked: it can only be read. 4.6 error cases if a wrong command or data is sent to the device, it generates an error condition by not sending the acknowledge after the first successive data or command. figure 4.5 shows the error sequence. the error case can be handled by using the readstatus command. this command can be sent after the error condition is detected; the device returns a status byte containing the error code. the readstatus command sequence is showed in figure 4.5 . the list of the error codes is illustrated in table 4.3 . remark: after the readstatus command execution or after any error, the start sequence must be carried out before sending a new command. the most significative bit of the error codes indicates (when set to ? 1 ? ) that the memory is locked. when a command, that is not allowed when the memory is locked, is sent, the ? not allowed ? code is sent. if another code is sent with the msb to ? 1 ? it indicates that the error condition is not caused by the memory lock, but by the event related with the code sent. warning: when the data writing into a non existing location is attempted, no error condition is generated. the user must take care in specifying the correct page address. wrong command/data case handling: s=start, p=stop, a=acknowledge, na=non-acknowledge from slave to master from master to slave wrong command/data a command/data na p s 1010000 0 a readstatus a p s ..... ..... 1010000 1 a status byte na p table 4.3 error codes name code description device locked xyyyyyyy x=lock bit (1=device locked), yyyyyyy=error code wrong command x0000101 the master sent a wrong command code not allowed x0000110 a command not allowed when the device is locked has been sent wrong mode x0010000 a code different form the programming mode code (00000000) has been sent
st52f510/f513/f514 41/137 4.7 in-situ programming (isp) the program/data memory can be programmed using the isp mode. this mode allows the device to be programmed when it is mounted in the user application board. this feature can be implemented by adding a minimum number of components and board impact. the programming procedures and pins used are identical to the ones described before for the standard programming mode. all the features previously described in this chapter are applicable in isp mode. if reset, scl and sda pins are used in the user application board for other purposes, it is recommended to provide an adequate isolation to avoid a conflict when the other devices force the signal level. the isp can be applied by using the standard tools for the device programming. the st52f510/f513 starter kit supplies a cable to perform the isp. the user application board should supply a suited connector type for the cable (see starter kit user manual). 4.8 in-application programming (iap) the in application programming mode (iap) allows the writing of user data in the flash and eeprom memories when the user program is running. there are two ways to write data in iap mode: single byte write and block write. both procedures take about 4.5 ms to complete the writing: the block write allows the writing of 32 byte in parallel. remark: during data writing, the execution of the user program is stopped until the procedure is completed. interrupt requests stop the writing operation and the data may be not stored. the bit abrt in the iap_sr input register signals that the data writing hasn ? t been completed. to assure writing completion, the user should globally disable the interrupts (udgi instruction) before starting iap data writing. 4.8.1 single byte write. writing of a single byte in the non-volatile program/data memory is performed by using the lder instructions (both direct and indirect addressing). the memory page should be indicated before the lder instruction with the pgset or pgsetr instruction. the byte address inside the page is specified by the lder instruction itself. as soon as the instruction is executed, the data writing starts and is performed in about 4.5 ms. 4.8.2 block write. this procedure allows the writing of 32 bytes in parallel. these bytes should belong to the same block. before the writing in the program/data memory, data must be buffered in the register file in the first 32 locations (0-31, 00h-020h) by using the normal instructions to load the register file locations. then the data writing starts by using the blkset instruction. the destination block is addressed by specifying the memory page with the pgset or pgsetr instruction before to start the writing; the block inside the page is addressed with the argument of the blkset instruction. example: pgset 5 blkset 4 this instruction sequence writes the contents of the first 32 bytes of the register file in the locations 1408-1439 (0580h-059fh). warning: the user should be careful in specifying the correct page and block: the addressing of an not existing block can cause the unwanted writing of a different block. as soon as the blkset instruction is executed, the data writing starts and is performed in about 4.5 ms. this procedure may also be used to write few data, taking in account that all the 32 byte are written in the block anyway. 4.8.3 memory corruption prevention. the user can protect some pages (or all the memory) from unintentional writings. the only constraint is that the protected pages must be consecutive. two option bytes allow the specification of the page to be protected: pg_lock (option byte 5) and pg_unlock (option byte 6). pg_lock is used to specify the first protected page; pg_unlock is used to specify the first page not protected after the protected ones. the pages between the two addresses are protected. when writing in a protected page is attempted, the procedure is aborted and the bit prtcd of iap_sr input register is set. if the pg_lock and pg_unlock have the same value, no page is protected. in programming mode the protection is not considered and the pages can be written unless the device is locked.
st52f510/f513/f514 42/137 4.8.4 option bytes. first protected page (pg_lock) option byte 5 (05h) bit 7-0: lck7-0 first page write protected in this register the address of first page to be protected in writing is specified. the pages following this one are protected up to the page specified by the pg_unlock option byte (not included among the protected ones). first page not protected (pg_unlock) option byte 6 (06h) bit 7-0: unlck7-0 first page not write protected in this register the address of first page not write protected after the protected ones is specified. the pages following this one aren ? t protected. 4.8.5 input register. iap status register (iap_sr) input register 40 (028h) read only reset value: 0000 0000 (00h) bit 7-2: not used bit 1: prtcd page protected 0: the writing has been completed 1: the writing has been aborted because the page is protected. bit 0: abrt writing operation aborted 0: the writing has been completed 1: the writing has been aborted because an interrupt or another unspecified cause occurred. the abrt and prtcd bits are reset after the next successful data writing in the flash of eeprom memory. 70 lck7 lck6 lck5 lck4 lck3 lck2 lck1 lck0 70 unlck7 unlck6 unlck5 unlck4 unlck3 unlck2 unlck1 unlck0 70 ------prtcdabrt
st52f510/f513/f514 43/137 5 interrupts the control unit (cu) responds to peripheral events and external events through its interrupt channels. when such events occur, if the related interrupt is not masked and doesn ? t have a priority order, the current program execution can be suspended to allow the cu to execute a specific response routine. each interrupt is associated with an interrupt vector that contains the memory address of the related interrupt service routine. each vector is located in the program/data memory space at a fixed address (see figure 3.2 program/data memory organization ). 5.1 interrupt processing if interrupts are pending at the end of an arithmetic or logic instruction, the interrupt with the highest priority is acknowledged. when the interrupt is acknowledged the flags and the current pc are saved in the stacks and the associated interrupt routine is executed. the start address of this routine (interrupt vector) is located in two bytes of the program/data memory, plus another byte for the jump or reti opcode, between address 3 and 32 (03h-020h). see table 5.1 for the list of the interrupt vector addresses. the interrupt routine is performed as a normal code. at the end of any instruction, the cu checks if a higher priority interrupt has sent an interrupt request. an interrupt request with a higher priority stops lower priority interrupts. the program counter and the flags are stored in their own stacks. with the instruction reti (return from interrupt) the flags and the program counter (pc) are restored from the top of the stacks. these stacks have already been described in paragraph 3.4 . an interrupt request cannot stop fuzzy rule processing. the request is acknowledged only after the end of a fuzzy rule or at the end of a logic or arithmetic instruction, unless a global interrupt disable instruction has been executed before. remark: a fuzzy routine can be interrupted only in the main program. when a fuzzy function is running inside another interrupt routine an interrupt request can cause side effects in the control unit. for this reason, in order to use a fuzzy function inside an interrupt routine, the user must include the fuzzy function between an udgi (mdgi) instruction and an uegi (megi) instruction (see the following paragraphs), in order to disable the interrupt request during the execution of the fuzzy function. figure 5.1 interrupt flow 5.2 global interrupt request enabling when an interrupt occurs, it generates a global interrupt pending (gip). after a gip a global interrupt request (gir) will be generated and interrupt service routine associated with the interrupt with higher priority will start. in order to avoid possible conflicts between the interrupt masking set in the main program, or inside high level language compiler macros, the gip is put in and through the user global interrupt mask or the macro global interrupt mask (see figure 5.2 ). the uegi/udgi instruction switches the user global interrupt mask enabling/disabling the gir for the main program. megi/mdgi instructions switch the macro global interrupt mask on/off in order to ensure that the macro will not be interrupted. figure 5.2 global interrupt request normal program flow interrupt service routine reti instruction interrupt global interrupt pending user global interrupt mask macro global global interrupt request
st52f510/f513/f514 44/137 5.3 interrupt sources st52f510/f513/f514 manages interrupt signals generated by the internal peripherals or generated by software by the trap instruction or coming from the port pins. there are two kinds of interrupts coming from the port pins: the nmi and the ports interrupts. nmi (not maskable interrupt) is associated with pin pa7 when it is configured as alternate function. this interrupt source doesn ? t have a configurable level priority and cannot be masked. the fixed priority level is lower than the software trap and higher than all the other interrupts. the nmi can be configured to be active on the rising or the falling edge. the port interrupts sources are connected with port a and port b pins. the pins belonging to the same port are associated with the same interrupt vector: there is one vector for port a and one for port b. in order to use one port pin as interrupt, it must be configured as an interrupt source (see i/o ports chapter). in this manner, up to 16 port interrupt sources are available. by reading the port the sources that belong to the same port can be discriminated. the port interrupts can be configured to be active on the rising or the falling edge, by using the int_pol register. warning: changing the nmi or port interrupt polarity an interrupt request is generated. all the interrupt sources are filtered, in order to avoid false interrupt requests caused by glitches. the trap instruction is something between a interrupt and a call: it generated an interrupt request at top priority level and the control is passed to the associated interrupt routine which vector is located in the fixed addresses 31-32. this routine cannot be interrupted and it is serviced even if the interrupts are globally disabled. note: similarly to the call instruction, after a trap the flags are not stacked. figure 5.3 example of interrupt requests 5.4 interrupt maskability and priority levels interrupts can be masked by the corresponding int_mask configuration register 0 (00h). an interrupt is enabled when the mask bit is ? 1". vice versa, when the bit is ? 0 ? , the interrupt is masked and the eventual requests are kept pending. all the interrupts, with the exception of the nmi and trap that have fixed level priority, have a configurable priority level. the configuration of the priority levels is completed by writing three consecutive configuration registers: int_prl_l, int_prl_m, int_prl_h, addresses from 2 to 4 (02h-04h). the 24 bits of these registers are divided into 8 groups of three bits: each group is associated with a priority level. the three bits of each group are written with the code number associated with the interrupt source. see table 5.1 to know the codes. warning: the priority levels configuration registers must be programmed with different values for each 3-bit groups to avoid erroneous operation. after the reset the priority registers are loaded with a default priority configuration. each time the priority is modified, each priority register must be configured with consistent values. during program execution the interrupt priority can only be modified within the main program: it cannot be changed within an interrupt service routine. in addition the interrupts must be disabled by means of the udgi instruction. in order to avoid side effect the interrupts must be disabled before the priority register configuration. 5.5 interrupt reset when an interrupt is masked, all requests are not acknowledged and remain pending. when the pending interrupt is enabled it is immediately serviced, if it has proper priority. this event may be undesired; in order to avoid this a rint instruction may be inserted followed by the code number that identifies the interrupt to reset the pending request. the rint instruction has no effect if the interrupt is being serviced see table 5.1 to know the codes. main program 5 4 3 2 1 0 int2 int0 int2 int1 int2 int3 int4 main program priority level int2 int0 int4 int1 int3 6
st52f510/f513/f514 45/137 5.6 register description interrupt mask register (int_mask) configuration register 0 (00h) read/write reset value: 0000 0000 (00h) bit 7: mskpb interrupt mask port b 0: port b interrupt masked 1: port b interrupt enabled bit 6: mskpa interrupt mask port a 0: port a interrupt masked 1: port a interrupt enabled bit 5: mski2c interrupt mask i 2 c interface 0: i 2 c interface interrupt masked 1: i 2 c interface interrupt enabled bit 4: mskspi interrupt mask spi 0: spi interrupt masked 1: spi interrupt enabled bit 3: msksci interrupt mask sci 0: sci interrupt masked 1: sci interrupt enabled bit 2: mskt1 interrupt mask pwm/timer 1 0: pwm/timer 1 interrupt masked 1: pwm/timer 1 interrupt enabled bit 1: mskt0 interrupt mask pwm/timer 0 0: pwm/timer 0 interrupt masked 1: pwm/timer 0 interrupt enabled bit 0: mskad interrupt mask a/d converter 0: a/d interrupt masked 1: a/d interrupt enabled interrupt polarity register (int_pol) configuration register 1 (01h) read/write reset value: 0000 0000 (00h) bit 7-5: not used bit 4-3: see timer 0 registers description bit 2: polpb port b interrupt polarity 0: the port b interrupt is triggered on the rising edge of the applied external signal. 1: the port b interrupt is triggered on the falling edge of the applied external signal. bit 1: polpa port a interrupt polarity 0: the port a interrupt is triggered on the rising edge of the applied external signal. 1: the port a interrupt is triggered on the falling edge of the applied external signal. bit 0: polnmi non maskable interrupt polarity 0: the nmi is triggered on the rising edge of the applied external signal. 1: the nmi is triggered on the falling edge of the applied external signal. low priority register (int_prl_l) configuration register 2 (02h) read/write reset value: 1111 1010 (fah) medium priority register (int_prl_m) configuration register 3 (03h) read/write reset value: 1100 0110 (c6h) 70 mskpb mskpa mski2c mskspi msksci mskt1 mskt0 mskad 70 - - - respol strpol polpb polpa polnmi 70 prl23 prl22 prl21 prl20 prl19 prl18 prl17 prl16 70 prl15 prl14 prl13 prl12 prl11 prl10 prl9 prl8
st52f510/f513/f514 46/137 high priority register (int_prl_h) configuration register 4 (04h) read/write reset value: 1000 1000 (088h) these three register are used to configure the priority level of each interrupt source. the 24 bits of these registers (prl23-prl0) are divided into 8 groups of three bits: each group is associated with a priority level (from level 1, the highest, to level 8, the lowest: level 0 is fixed for the nmi that can be interrupted only by the trap) . the three bits of each group are written with the code number associated with the interrupt source (see table 5.1 ). prl2-prl0 : interrupt priority level 1 (highest) prl5-prl3 : interrupt priority level 2 prl8-prl6 : interrupt priority level 3 prl11-prl9 :interrupt priority level 4 prl14-prl12 : interrupt priority level 5 prl17-prl15 : interrupt priority level 6 prl20-prl18 : interrupt prioritylevel 7 prl23-prl21 : interrupt priority level 8 (lowest) example: writing the code 110 into prl8-prl6 bits the priority level 3 is assigned to the port a interrupt. warning: the priority level configuration registers must be always configured with consistent values. 70 prl7 prl6 prl5 prl4 prl3 prl2 prl1 prl0 table 5.1 interrupt sources paramethers interrupt source priority type prl code rint code maskable vector addresses a/d converter programmable 000 0 yes 3-5 (03h-05h) pwm/timer 0 programmable 001 1 yes 6-8 (06h-08h) pwm/timer 1 programmable 010 2 yes 9-11 (09h-0bh) sci programmable 011 3 yes 12-14 (0ch-0eh) spi programmable 100 4 yes 15-17 (0fh-011h) i 2 c interface programmable 101 5 yes 18-20 (012h-014h) port a programmable 110 6 yes 21-23 (015h-017h) port b programmable 111 7 yes 24-26 (018h-01ah) nmi fixed - 8 no 27-29 (01bh-01dh) trap fixed to highest - - no 30-32 (01eh-020h)
st52f510/f513/f514 47/137 6 clock, reset & power saving modes 6.1 clock the st52f510/f513/f514 clock generator module generates the internal clock for the internal control unit, alu and on-chip peripherals. the clock is designed to require a minimum of external components. st52f510/f513/f514 devices supply the internal oscillator in four clock modes: external oscillator external clock internal clock the device always starts in internal clock mode, excluding any external clock source. after the start-up phase the clock is configured according to the user definition programmed in the option byte 0 (osc_cr). the internal clock generator can supply an internal clock signal with a fixed frequency of 10 mhz 1%, without the need for external components. in order to obtain the maximum accuracy, the frequency can be calibrated by configuring the related option byte 2 (osc_set). the external oscillator mode uses a quartz crystal or a ceramic resonator connected to oscin and oscout as illustrated in figure 6.1 . this figure also illustrates the connection of an external clock. the st52f510/f513/f514 oscillator circuit generates an internal clock signal with the same period and phase as the oscin input pin. the maximum frequency allowed is 20 mhz. when the external oscillator is used, the loop gain can be adapted to the various frequencies values by configuring the three bits of the option byte 1 clk_set (see register decription, table 6.1 ). when an external clock is used, it must be connected to the pin oscin while oscout can be floating. in this case, option byte 1 bits must be written with 0 (000). the crystal oscillator start-up time is a function of many variables: crystal parameters (especially r s ), oscillator load capacitance (cl), ic parameters, environment temperature and supply voltage. the crystal or ceramic leads and circuit connections must be as short as possible. typical values for cl1, cl2 are 10pf for a 20 mhz crystal. figure 6.1 illustrates the possible connections. the clock signal generates two internal clock signals: one for the cpu and one for the peripherals. the cpu clock frequency can be reduced, in order to decrease current consuption, by setting the cpu_clk configuration register 46 (02eh). the cpu clock can be reduced up to 64 times (see register description). figure 6.1 oscillator connections oscin oscout st five oscin st five oscout crystal clock external clock cl1 10pf cl2 10pf clock input
st52f510/f513/f514 48/137 6.2 reset four reset sources are available: reset pin (external source) watchdog (internal source) power on reset (internal source) plvd reset (internal source) when a reset event occurs, the user program restarts from the beginning. 6.2.1 external reset. reset is an input pin. an internal reset does not affect this pin. a reset signal originated by external sources is recognized immediately. the reset pin may be used to ensure vdd has risen to a point where the icu can operate correctly before the user program is run. reset must be set to vdd in working mode. an internal pull up resistor guarantees that the reset pin is at level ? 1 ? when no halt or power- on events occur. see table 16.9 and table 16.15 for more details. 6.2.2 reset procedures. after the reset pin is set to vdd or following a power-on reset event, the device is not started until the external supply voltage has reached a threshold level (typical value vdd=2.6 v, see electrical characteristics). figure 6.2 reset block diagram after this level has been reached, the internal oscillator (10 mhz) is started and a delay period of 4096 clock cycles is initiated, in order to allow the oscillator to stabilize and to ensure that recovery has taken place from the reset state. if the device has been configured to work with the internal clock, the user program starts, otherwise the option byte 7 (wakeup) is read and another count starts before running the user program. the duration of the count depends on the contents of the option byte 7 (wakeup), that works as a prescaler, according to the follwing formula: this delay has been introduced in order to ensure that the oscillator has become stable after its restart. if the reset is generated by the plvd or the watchdog, the oscillator is not turned off; for this reason the cpu is then restarted immediately, without the delay. after a reset procedure is completed, the core reads the instruction stored in the first 3 bytes of the program/data memory, which contains a jump instruction to the first instruction of the user program. the assembler tool automatically generates this jump instruction with the first instruction address. power-on reset vdd reset 4096 x tclk internal reset watchdog reset (wakeup+1) x 4096 x tclk watchdog programmable low voltage detector reset plvd ckmod1:0 internal clock sources external clock tclk = internal clock period (100 ns) ckmod1:0 = see option byte 0 (osc_cr) wakeup = see option byte 7 (wakeup) delay 4096 wakeup 1 + () tclk =
st52f510/f513/f514 49/137 6.3 programmable low voltage detector the on-chip programmable low voltage detector (plvd) circuit prevents the processor from falling into an unpredictable status if the power supply drops below a certain level. when vdd drops below the detection level, the plvd causes an internal processor reset that remains active as long as vdd remains below the trigger level. the plvd resets the entire device except the power-on detector and the plvd itself. the plvd can be enabled/disabled at reset by setting the option byte 3 (plvd_cr) bits. when vdd increases above the trigger level, the plvd reset is deactivated and the user program is started from the beginning. the detection levels are programmable by means of the option byte 3 (plvd_cr). there are three levels for the plvd falling voltages (2.9v, 3.4v, 3.9v) and for rising voltages (3.1v, 3.65v, 4.2v). the hysteresis for each level are respectively 200 mv, 250 mv and 300 mv. the plvd circuit will only detect a drop if vdd voltage stays below the safe threshold for at least 5 s before activation/deactivation of the plvd in order to filter voltage spikes. remark: the plvd function isn ? t active when it is in halt mode. in that case the device is reset if the vdd voltage stays below the threshold of power on reset. 6.4 power saving modes there are two types of power saving modes: wait and halt mode. these conditions may be entered by using the wait or halt instructions. 6.4.1 wait mode. wait mode places the icu in a low power consumption status by stopping the cpu. all peripherals and the watchdog remain active. during wait mode the interrupts are enabled. the icu remains in wait mode until an interrupt or a reset occurs, whereupon the program counter jumps to the interrupt service routine or, if a reset occurs, to the beginning of the user program. 6.4.2 halt mode. halt mode is the lowest icu power consumption mode, which is entered by executing the halt instruction. the internal oscillator is turned off, causing all internal processing to be terminated, including the operations of the on-chip peripherals. halt mode cannot be used when the watchdog is enabled. if the halt instruction is executed while the watchdog system is enabled, it will be skipped without modifying the normal cpu operations. the icu can exit halt mode upon reception of an nmi, a port interrupt or a reset. the internal oscillator (10 mhz) is started and a delay period of 4.096 clock cycles is initiated, in order to allow the oscillator to stabilize and to ensure that recovery has taken place from the reset state. if the device has been configured to work with the internal clock, the user program is started, otherwise the option byte 7 (wakeup) is read and another count is started before running the user program. the count duration depends on the contents of the option byte 7 (wakeup), that works as prescaler, according to the follwing formula: this delay has been introduced in ordet to ensure that the oscillator has become stable after it is restarted. after the start up delay, by exiting with the nmi or a port interrupt, the cpu restarts operations by serving the associated interrupt routine. note: if the port interrupt is masked, the icu doesn ? t exit the halt mode with this interrupt. figure 6.3 wait flow chart delay 4096 wakeup 1 + () tclk = oscillator peripherals clock cpu clock interrupts on on off enab. wait istruction reset interrupt yes no cpu clock on program counter reset no jump to int. routine cpu clock on normal program flow
st52f510/f513/f514 50/137 figure 6.4 halt flow chart halt instruction watchdog enabled halt instruction skipped yes no oscillator off peripherals clock off cpu clock off restart program servicing the interrupt routine nmi or port interrupt no yes no yes reset reset cpu and restart user program oscillator on peripherals clock on cpu clock on 4096 internal clock cycles delay oscillator on peripherals clock on cpu clock on 4096 internal clock cycles delay yes no internal clock ? internal clock ? 4096 x (wakeup+1) clock cycles delay 4096 x (wakeup+1) clock cycles delay no yes port interrupt masked no yes
st52f510/f513/f514 51/137 6.5 register description the following section describes the register which are used to configure the clock, reset and plvd. 6.5.1 configuration register. cpu clock prescaler (cpu_clk) configuration register 46 (02eh) read/write reset value: 0000 0000 (00h) bit 7-6: not used bit 5-0: cpuck5-0 cpu clock prescaler bits the cpu clock frequency is divided by a factor described in the following table 6.5.2 option bytes. clock mode (osc_cr) option byte 0 (00h) bit 7-2: not used bit 1: must be set to 0 bit 0: ckmod clock mode 0: internal oscillator 1: external clock or quartz external clock parameters (clk_set) option byte 1 (01h) bit 7-3: not used bit 2-0: ckpar2-0 oscillator gains these three bits enable/disable the loop gains when a external clock or quartz are used for generating the clock. the following table decribes the possible configuration options. table 6.1 illustrates the reccomended values for the most common frequencies used, time to start the oscillations and the settling time to have a duty cycle of 40%-60% (at steady state it is 50%). warning: if an external clock is used instead of a quartz or ceramic resonator, it is reccomended that no gain be enabled (ckpar2-0=000) in order lo lower the current consumption. 70 - - cpuck5 cpuck4 cpuck3 cpuck2 cpuck1 cpuck0 cpuck5-0 cpu clock 000000 f cpu =f osc 000001 f cpu =f osc /2 000010 f cpu =f osc /4 000100 f cpu =f osc /8 001000 f cpu =f osc /16 010000 f cpu =f osc /32 100000 f cpu =f osc /64 others f cpu =f osc /64 70 -------ckmod 70 - - - - - ckpar2 ckpar1 ckpar0 ckpar2-0 enabled gain stages 000 no gains (external clock mode) 001 1 gain stage enabled 010 not allowed 011 3 gain stage enabled 100 not allowed 101 6 gain stage enabled 110 not allowed 111 8 gain stage enabled
st52f510/f513/f514 52/137 internal oscillator calibration (osc_set) option byte 2 (02h) bit 7-6: not used bit 5-0: ospar5-0 internal oscillator parameters these bits are used in order to calibrate the precision of the internal oscillator working at 10 mhz. the six bits enable some current generators with steps of 0.05 a corresponding to interval of frequency of 100khz . warning: the maximum configuration value allowed is 101000 (40). the value corresponding to the 10 mhz by design is 010100 (20). loading values over 40 the oscillator is stopped. plvd control register (plvd_cr) option byte 3 (03h) bit 7-2: not used bit 1-0: plvd1-0 plvd detection levels 00: lowest detection level 01: highest detection level 10: plvd disabled 11: medium detection level wake-up time prescaler (wakeup) option byte 7 (07h) bit 7-0: wk7-0 wake-up prescaler this byte determinates the time delay for the stabilization of the oscillator after an external reset or a por and after the wake-up from halt. the time delay is computed according to the following formula: warning: if the internal clock is used as clock source the prescaler is not used. table 6.1 recomended gain stages for the most common frequencies frequency recommend gain stages 1) ckpar2-0 oscillation start times 2) settling times for 40% duty-cycle 2) external clock 0 000 - - 1 mhz 1 001 367 s27 s 4 mhz 1 001 84 s10 s 8 mhz 3 011 75 s9 s 10 mhz 3 011 79 s5 s 12 mhz 6 101 110 s8 s 16 mhz 6 101 352 s7 s 20 mhz 8 111 165 s11 s (1) the recommended values have been chosen to have the best tradeoff beetwen start time and current consumption. higher gains give shorter start times; lower gains give less current consumption. (2) indicative values by design at 25 celsius, v dd =2.6 v. not tested in production. 70 - - ospar5 ospar4 ospar3 ospar2 ospar1 ospar0 70 ------plvd1plvd0 70 wk7 wk6 wk5 wk4 wk3 wk2 wk1 wk0 delay 4096 wakeup 1 + () tclk =
st52f510/f513/f514 53/137 7 i/o ports 7.1 introduction st52f510/f513/f514 are characterized by flexible individually programmable multi-functional i/o lines. the st52f510/f513/f514 supplies devices with up to 3 ports (named from a to c) with up to 22 i/o lines. each pin can be used as a digital i/o or can be connected with a peripheral (alternate function). the i/o lines belonging to port a and port b can also be used to generate port interrupts. the i/o port pins can be configured in the following modes: input high impedance (reset state) input with pull-up output with pull-up output push-pull output with weak pull-up output open drain interrupt with pull-up interrupt without pull-up these eight modes can be selected by programming three configuration registers for each port. all the pins that belong to the same port can be configured separately by setting the corresponding bits in the three registers (see register description). to avoid side effects, the configuration registers are latched only when the data direction register (port_x_ddr) is written. for this reason this register must be always written when modifying the pin configuration. all the i/o digital pins are ttl compatible and have a schmitt trigger. the output buffer can supply high current sink (up to 8ma). note: with the aim to reduce current consumption it is recommended that no floating pins are left; all unused pins must be kept at fixed voltage. furtehrmore it is recommended that bits of io configuration registers related to not used or non available port/pins are set as input pull-up. figure 7.1 digital pin 7.2 input mode the pins configured as input can be read by accessing the corresponding port input register by means of the ldri instruction. the addresses for port a , b and c are respectively 0 (00h), 1 (01h), and 2 (02h). when executing the ldri instruction all the signals connected to the input pins of the port are read and the logical value is copied in the specified register file location. if some pins are configured in output, the port buffer contents, which are the last written logical values in the output pins, are read. 7.3 output mode the pins configured as output can be written by accessing the corresponding port output register by means of the ldpr, ldpi and ldpe instructions. the addresses for port a , b and c are respectively, 0 (00h), 1 (01h), and 2 (02h). when executing the above mentioned instructions, the port buffer is written and the port pin signals are modified. if some pins are configured as input or as interrupt, the values are ignored. 7.4 interrupt mode the pins configured as interrupt mode can generate a port interrupt request. only port a and port b pins can be configured in this mode. an interrupt vector is associated to each port: there are two port interrupts available but more pins of the ports can act as source at the same time. the configuration registers switch the signals deriving from interrupt pins to an or gate that generates the interrupt request signal. the signal deriving from the pins can be read, allowing the discrimination of the interrupt sources when more than one pin can generate the interrupt signal. the interrupt trigger can be configured either in the rising or falling edge of the external signal by using the int_pol register figure 7.2 analog pin pad pull up enable digital out enable data out port a,c,d,e pin data in
st52f510/f513/f514 54/137 7.5 alternate functions the alternate function allows the pins to be connected with the peripheral signals or nmi. not all port pins have an alternate function associated. a configuration register (port_x_af) for each port is used to switch from the digital i/o function or the alternate function. some pins can have two alternate functions: one input function and one output function. to switch between the two functions, the port_x_af must be configured in alternate function mode and the port_x_ddr configuration register must be switched in input mode or in output mode. nmi is considered an alternate function. for this reason an nmi interrupt request can ? t be generated unless the pa7 pin is configured in alternate function and in one of the input modes. figure 7.3 port pin architecture when an on-chip peripheral is configured to use a pin, the correct i/o mode of the related pin should be selected by selecting one of the appropriate modes. see the registers description in order to obtain the right configurations.some peripherals, as for example the i 2 c peripheral, directly drive the pin configuration according to the current function, overriding the user configuration. 7.6 register description in order to configure the port ? s pins, the three configuration registers port_x_pullup, port_x_or and port_x_ddr must be configured. the combination of these three registers determine the pin ? s configuration, according to the scheme shown in table 7.1 . in order to select between the digital functions or alternate functions port_x_af register must be configured. each bit of the configuration registers configures the pin of the corresponding position (example: port_a_ddr bit 5 configures the pin pa5). conf. reg. d e c o d e r ff register file alternate function interrupt polarity irq to input register vdd digital port pin int pu sel en enable data conf. reg. conf. reg. conf. reg.
st52f510/f513/f514 55/137 7.6.1 configuration registers. port a pull-up register (port_a_pullup) configuration register 24 (018h) read/write reset value: 0000 0000 (00h) bit 7-0: pua7-0 port a pull-up (see table 7.1) 0: port a pin without pull-up 1: port a pin with pull-up port a option register (port_a_or) configuration register 25 (019h) read/write reset value: 0000 0000 (00h) bit 7-0: ora7-0 port a option (see table 7.1) port a data direction register (port_a_ddr) configuration register 26 (01ah) read/write reset value: 0000 0000 (00h) bit 7-0: ddra7-0 port a direction (see table 7.1) 0: port a pin configured as input 1: port a pin configured as output port a alternate fuction (port_a_af) configuration register 27 (01bh) read/write reset value: 0000 0000 (00h) bit 7: afa7 alternate function pa7 0: digital i/o 1: int bit 6: afa6 alternate function pa6 0: digital i/o 1: t0out bit 5: afa5 alternate function pa5 0: digital i/o 1: tclk bit 4: afa4 alternate function pa4 0: digital i/o 1: tstrt bit 3: afa3 alternate function pa3 0: digital i/o 1: rx bit 2: afa2 alternate function pa2 0: digital i/o 1: t1out bit 1: afa1 alternate function pa1 0: digital i/o 1: sda bit 0: afa0 alternate function pa0 0: digital i/o 1: scl 70 pua7 pua6 pua5 pua4 pua3 pua2 pua1 pua0 70 ora7 ora6 ora5 ora4 ora3 ora2 ora1 ora0 70 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 70 afa7 afa6 afa5 afa4 afa3 afa2 afa1 afa0 table 7.1 pin mode configuration mode pu or ddr input high impedance 0 0 0 input with pull-up 1 0 0 interrupt without pull-up 0 1 0 interrupt with pull-up 1 1 0 output push-pull 0 0 1 output with pull-up 1 0 1 output open drain 0 1 1 output weak pull-up 1 1 1
st52f510/f513/f514 56/137 port b pull-up register (port_b_pullup) configuration register 28 (01ch) read/write reset value: 0000 0000 (00h) (*) pin not available in 16/20 pin package devices. set to ? 1 ? (**) pin not available in 16 pin package devices. set to ? 1 ? bit 7-0: pub7-0 port b pull-up (see table 7.1) 0: port b pin without pull-up 1: port b pin with pull-up port b option register (port_b_or) configuration register 29 (01dh) read/write reset value: 0000 0000 (00h) (*) pin not available in 16/20 pin package devices. set to ? 0 ? (**) pin not available in 16 pin package devices. set to ? 0 ? bit 7-0: orb7-0 port b option (see table 7.1) port b data direction register (port_b_ddr) configuration register 30 (01eh) read/write reset value: 0000 0000 (00h) (*) pin not available in 16/20 pin package devices. set to ? 0 ? (**) pin not available in 16 pin package devices. set to ? 0 ? bit 7-0: ddrb7-0 port b direction (see table 7.1) 0: port b pin configured as input 1: port b pin configured as output port b alternate fuction (port_b_af) configuration register 31 (01fh) read/write reset value: 0000 0000 (00h) bit 7: afb7 alternate function pb7 0: digital i/o 1: ain7 bit 6: afb6 alternate function pb6 0: digital i/o 1: ain6 bit 5: afb5 alternate function pb5 0: digital i/o 1: ain5 bit 4: afb4 alternate function pb4 0: digital i/o 1: ain4 bit 3: afb3 alternate function pb3 0: digital i/o 1: ain3 bit 2: afb2 alternate function pb2 0: digital i/o 1: ain2 bit 1: afb1 alternate function pb1 0: digital i/o 1: ain1 bit 0: afb0 alternate function pb0 0: digital i/o 1: ain0 / vref port c pull-up register (port_c_pullup) configuration register 32 (020h) read/write reset value: 0000 0000 (00h) note: the corresponding pins are not available in 16/20 pin devices. bit 7-6: not used bit 5-0: puc5-0 port c pull-up (see table 7.1) 0: port c pin without pull-up 1: port c pin with pull-up 70 pub7* pub6* pub5** pub4** pub3** pub2** pub1 pub0 70 orb7* orb6* orb5** orb4** orb3** orb2** orb1 orb0 70 ddrb7* ddrb6* ddrb5** ddrb4** ddrb3** ddrb2** ddrb1 ddrb0 70 afb7 afb6 afb5 afb4 afb3 afb2 afb1 afb0 70 - - puc5 puc4 puc3 puc2 puc1 puc0
st52f510/f513/f514 57/137 port c option register (port_c_or) configuration register 33 (021h) read/write reset value: 0000 0000 (00h) note: the coresponding pins are not available in 16/20 pin devices. bit 7-6: not used bit 5-0: orc5-0 port c option (see table 7.1) port c data direction register (port_c_ddr) configuration register 34 (022h) read/write reset value: 0000 0000 (00h) note: the coresponding pins are not available in 16/20 pin devices. bit 7-6: not used bit 5-0: ddrc5-0 port c direction (see table 7.1) 0: port c pin configured as input 1: port c pin configured as output note: in order to achieve low current consuption, the port pins must be configured as input pull-up, even though they are not existing in the package. for example in 20 pin devices, the pins pb6-7 and pc0-7 must be configured in input pull-up. port c alternate fuction (port_c_af) configuration register 35 (023h) read/write reset value: 0000 0000 (00h) note: the coresponding pins are not available in 16/20 pin devices. bit 7-6: not used bit 5: afc5 alternate function pc5 0: digital i/o 1: tres bit 4: afc4 alternate function pc4 0: digital i/o 1: tx bit 3: afc3 alternate function pc3 0: digital i/o 1: ss bit 2: afc2 alternate function pc2 0: digital i/o 1: miso bit 1: afc1 alternate function pc1 0: digital i/o 1: mosi bit 0: afc0 alternate function pc0 0: digital i/o 1: sck 7.6.2 input registers. port a data input register (port_a_in) input register 0 (00h) read only reset value: xxxx xxxx bit 7-0: pai7-0 port a input data the logical level applied in the port a pins, configured as digital input, can be achieved by reading this register. port b data input register (port_b_in) input register 1 (01h) read only reset value: xxxx xxxx (*) not used in 16/20 pin package devices (**) not used in 16 pin package devices 70 - - orc5 orc4 orc3 orc2 orc1 orc0 70 - - ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 70 - - afc5 afc4 afc3 afc2 afc1 afc0 70 pai7 pai6 pai5 pai4 pai3 pai2 pai1 pai0 70 p bi 7* pbi6* pbi5** pbi4** pbi3** pbi2** pbi1 pbi0
st52f510/f513/f514 58/137 bit 7-0: pbi7-0 port b input data the logical level applied in the port b pins, configured as digital input, can be achieved by reading this register. port c data input register (port_c_in) input register 2 (02h) read only reset value: xxxx xxxx note: this register is not used in 16/20 pin devices bit 7-6: not used bit 5-0: pci5-0 port c input data the logical level applied in the port c pins, configured as digital input, can be achieved by reading this register. 7.6.3 output registers. port a data output register (port_a_out) output register 0 (00h) write only reset value: 0000 0000 (00h) bit 7-0: pao7-0 port a output data the logical values written in these register bits are put in the port a pins configured as digital output. port b data output register (port_b_out) output register 1 (01h) write only reset value: 0000 0000 (00h) (*) not used in 16/20 pin package devices (**) not used in 16 pin package devices bit 7-0: pbo7-0 port b input data the logical values written in these register bits are put in the port b pins configured as digital output. port c data output register (port_c_out) output register 2 (02h) write only reset value: 0000 0000 (00h) note: this register is not used in 16/20 pin devices bit 7-6: not used bit 5-0: pco5-0 port c input data the logical values written in these register bits are put in the port c pins configured as digital output. 70 - - pci5 pci4 pci3 pci2 pci1 pci0 70 pao7 pao6 pao5 pao4 pao3 pao2 pao1 pao0 70 p bo 7* pbo6* pbo5** pbo4** pbo3** pbo2** pbo1 pbo0 70 - - pco5 pco4 pco3 pco2 pco1 pco0
st52f510/f513/f514 59/137 8 fuzzy computation (dp) the st52f510/f513/f514 decision processor (dp) main features are: up to 8 inputs with 8-bit resolution; 1 kbyte of program/data memory available to store more than 300 to membership functions (mbfs) for each input; up to 128 outputs with 8-bit resolution; possibility of processing fuzzy rules with an unlimited number of antecedents; unlimited number of rules and fuzzy blocks. the limits on the number of fuzzy rules and fuzzy program blocks are only related to the program/data memory size. 8.1 fuzzy inference the block diagram shown in figure 8.1 describes the different steps performed during a fuzzy algorithm. the st52f510/f513/f514 core allows for the implementation of a mamdami type fuzzy inference with crisp consequents. inputs for fuzzy inference are stored in 8 dedicated fuzzy input registers. the ldfr instruction is used to set the input fuzzy registers with values stored in the register file. the result of a fuzzy inference is stored directly in a location of the register file. 8.2 fuzzyfication phase in this phase the intersection (alpha weight) between the input values and the related mbfs (see figure 8.2 ) is performed. eight fuzzy input registers are available for fuzzy inferences. figure 8.1 fuzzy inference figure 8.2 alpha weight calculation after loading the input values by using the ldfr assembler instruction, the user can start the fuzzy inference by using the fuzzy assembler instruction. during fuzzyfication: input data is transformed in the activation level (alpha weight) of the mbf ? s. 8.3 inference phase the inference phase manages the alpha weights obtained during the fuzzyfication phase to compute the truth value ( ) for each rule. this is a calculation of the maximum (for the or operator) and/or minimum (for the and operator) performed on alpha values according to the logical connectives of fuzzy rules. several conditions may be linked together by linguistic connectives and/or, not operators and brackets. the truth value and the related output singleton are used by the defuzzyfication phase, in order to complete the inference calculation. 11 1m n1 nm fuzzyfication inference phase defuzzyfication n rules n rules -1 2 1 input values output values 1 ij j-th mbf i-th input variable
st52f510/f513/f514 60/137 figure 8.3 fuzzyfication 8.4 defuzzyfication in this phase the output crisp values are determined by implementing the consequent part of the rules. each consequent singleton x i is multiplied by its weight values i , calculated by the decision processor, in order to compute the upper part of the defuzzyfication formula. each output value is obtained from the consequent crisp values (x i ) by carrying out the following defuzzyfication formula: where: i = identifies the current output variable n = number of the active rules on the current output ij = weight of the j-th singleton x ij = abscissa of the j-th singleton the decision processor outputs are stored in the ram location i-th specified in the assembler instruction out i. 8.5 input membership function the decision processor allows the management of triangular mbfs. in order to define an mbf, three different parameters must be stored on the program/data memory (see figure 8.4 ): the vertex of the mbf: v ; the length of the right semi-base: rvd ; the length of the left semi-base: lvd ; in order to reduce the size of the memory area and the computational effort the vertical range of the vertex is fixed between 0 and 15 (4 bits) by using the previous memorization method different kinds of triangular membership functions may be stored. figure 8.5 shows some examples of valid mbfs that can be defined in st52f510/ f513/f514. each mbf is then defined storing 3 bytes in the first kbyte of the program/data memory. the mbf is stored by using the following instruction: mbf n_mbf lvd v rvd where: n_mbf is a tag number that identifies the mbf lvd , v , and rvd are the parameters that describe the mbf ? s shape as described above. figure 8.4 mbfs parameters input 1 x1 1 input 2 x2 2 or = max if input 1 is x1 or input 2 is x2 then ....... input 1 x1 1 input 2 x2 2 if input 1 is x1 and input 2 is x2 then ....... y i x ij ij j n ij j n --------------------- = x 15 lvd rvd v 15 0 0 input mbf output singleton output variable input variable w
st52f510/f513/f514 61/137 figure 8.5 example of valid mbfs 8.6 output singleton the decision processor uses a particular kind of membership function called singleton for its output variables. a singleton doesn ? t have a shape, like a traditional mbf, and is characterized by a single point identified by the couple (x, w), where w is calculated by the inference unit as described earlier. often, a singleton is simply identified with its crisp value x. figure 8.6 output membership functions 8.7 fuzzy rules rules can have the following structures: if a op b op c...........then z if (a op b) op (c op d op e...) ...........then z where op is one of the possible linguistic operators (and/or) in the first case the rule operators are managed sequentially; in the second one, the priority of the operator is fixed by the brackets. each rule is codified by using an instruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds at 20 mhz. the assembler instruction set used to manage the fuzzy operations is reported in the table below. 1 i-th output 0 x ij x i0 x in i0 ij in j-th singleton table 8.1 fuzzy instructions set instruction description mbf n_mbf ivd v rvd stores the mbf n_mbf with the shape identified by the parameters ivd , v and rvd is n m fixes the alpha value of the input n with the mbf m isnot n m calculates the complementary alpha value of the input n with the mbf m. fzand implements the fuzzy operation and fzor implements the fuzzy operation or con crisp multiplies the crisp value with the last weight out n_out performs defuzzyfication and stores the currently fuzzy output in the register n_out fuzzy starts the computation of a sigle fuzzy variable ( ) modify the priority in the rule evaluation
st52f510/f513/f514 62/137 example 1 : if input 1 is not mbf 1 and input 4 is mbf 12 or input 3 is mbf 8 then crisp 1 is codified by the following instructions: example 2 , the priority of the operator is fixed by the brackets: if (input 3 is mbf 1 and input 4 is not mbf 15 ) or (input 1 is mbf 6 or input 6 is not mbf 14 ) then crisp 2 at the end of the fuzzy rules related to the current fuzzy variable, by using the instruction out reg , the specified register is written with the computed value. afterwards, the control of the algorithm returns to the cu. the next fuzzy variable evaluation must start again with a fuzzy instruction. isnot 1 1 calculates the not value of input 1 with mbf 1 and stores the result in internal registers fzand implements the operation and between the previous and the next alpha value evaluated is 4 12 fixes the value of input 4 with mbf 12 and stores the result in internal registers fzor implements the operation or between the previous and the next alpha value evaluated is 3 8 fixes the value of input 3 with mbf 8 and stores the result in internal registers con crisp 1 multiplies the result of the last ? operation with the crisp value crisp 1 ( parenthesis open to change the priority is 3 1 fixes the value of input 3 with mbf 1 and stores the result in internal registers fzand implements the operation and between the previous and the next alpha value evaluated isnot 4 15 calculates the not value of input 4 with mbf 15 and stores the result in internal registers ) parenthesis closed fzor implements the operation or between the previous and the next alpha value evaluated ( parenthesis open to change the priority is 1 6 fixes the value of input 1 with mbf 6 and stores the result in internal registers fzor implements the operation or between the previous and the next alpha value evaluated isnot 2 14 calculates the not value of input 6 with mbf 14 and stores the result in internal registers ) parenthesis closed con crisp 2 multiplies the result of the last ? operation with the crisp value crisp 2
st52f510/f513/f514 63/137 9 instruction set st52f510/f513/f514 supplies 107 (98 + 9 fuzzy) instructions that perform computations and control the device. computational time required for each instruction consists of one clock pulse for each cycle plus 2 clock pulses for the decoding phase. total computation time for each instruction is reported in table 9.1 the alu of st52f510/f513/f514 can perform multiplication (mult) and division (div). multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values), see figure 2.3 . division is performed between a 16 bit dividend and an 8 bit divider, the result and the remainder are stored in two 8-bit registers (see figure 2.4 ). 9.1 addressing modes st52f510/f513/f514 instructions allow the following addressing modes: inherent: this instruction type does not require an operand because the opcode specifies all the information necessary to carry out the instruction. examples: nop, scf. immediate: these instructions have an operand as a source immediate value. examples: ldrc, addi. direct: the operands of these instructions are specified with the direct addresses. the operands can refer (according to the opcode) to addresses belonging to the different addressing spaces. example: sub, ldre. indirect: data addresses that are required are found in the locations specified as operands. both source and/or destination operands can be addressed indirectly. the operands can refer, (according to the opcode) to addresses belonging to different addressing spaces. examples: ldrr(reg1),(reg2); lder mem_addr,(reg1). bit direct: operands of these instructions directly address the bits of the specified register file locations. examples: bset, btest. 9.2 instruction types st52f510/f513/f514 supplies the following instruction types: load instructions arithmetic and logic instructions bitwise instructions jump instructions interrupt management instructions control instructions the instructions are listed in table 9.1 table 9.1 instruction set load instructions mnemonic instruction bytes cycles z s c blkset blkset const 2 (*) - - - getpg getpg regx 2 7 - - - ldce ldce confx,memy 3 8/10 - - - ldci ldci confx, const 3 7 - - - ldcnf ldcnf regx, conf 3 7 - - - ldcr ldcr confx, regy 3 8 - - - lder lder memx, regy 3 11 - - - lder lder (regx),(regy) 3 12 - - - lder lder (regx), regy 3 11 - - - lder lder memx,(regy) 3 12 - - - ldfr ldfr fuzzyx, regy 3 8 - - -
st52f510/f513/f514 64/137 ldpe ldpe outx, memy 3 8/10 - - - ldpe ldpe outx, (regy) 3 9/11 - - - ldpi ldpi outx, const 3 7 - - - ldpr ldpr outx, regy 3 8 - - - ldrc ldrc regx, const 3 7 - - - ldre ldre regx, memy 3 8/10 - - - ldre ldre (regx), (regy) 3 10/12 - - - ldre ldre (regx), memy 3 9/11 - - - ldre ldre regx, (regy) 3 9/11 - - - ldri ldri regx, inpx 3 7 - - - ldrr ldrr regx, regy 3 9 - - - ldrr ldrr (regx), (regy) 3 10 - - - ldrr ldrr (regx), regy 3 9 - - - ldrr ldrr regx, (regy) 3 10 - - - pgset pgset const 2 4 - - - pgsetr pgsetr regx 2 5 - - - pop pop regx 2 7 - - - push push regx 2 8 - - - load instructions (continued) arithmetic instructions mnemonic instruction bytes cycles z s c add add regx, regy 3 9 i - i addc addc regx, regy 3 9 i - i addi addi regx, const 3 8 i - i addic addic regx, const 3 8 i - i addo addo regx, regy 3 11 i i i addoc addoc regx, regy 3 11 i i i addoi addoi regx, const 3 10 i i i addoic addoicregx,const 3 10 i i i and and regx, regy 3 9 i - - andi andi regx,const 3 8 i - - cp cp regx, regy 3 8 i i - cpi cpi regx,const 3 7 i i - dec dec regx 2 7 i i -
st52f510/f513/f514 65/137 div div regx, regy 3 16 i i i inc inc regx 2 7 i - i mirror mirror regx 2 7 i - - mult mult regx, regy 3 11 i - - not not regx 2 7 i - - or or regx, regy 3 9 i - - ori ori regx, const 3 8 i - - sub sub regx, regy 3 9 i i - subi subi regx, const 3 8 i i - subis subis regx, const 3 8 i i - subo subo regx, regy 3 11 i i i suboi suboi regx, const 3 10 i i i subois suboisregx,const 3 10 i i i subos subos regx, regy 3 11 i i i subs subs regx, regy 3 9 i i - rcf rcf 1 4 - - i rsf rsf 1 4 - i - rzf rzf 1 4 i - - scf scf 1 4 - - i ssf ssf 1 4 - i - szf szf 1 4 i - - xor xor regx, regy 3 9 i - - xori xori regx, cons 3 8 i - - bitwise instructions mnemonic instruction bytes cycles z s c asl asl regx 2 7 i - i asr asr regx 2 7 i i - bnot bnot regx, bit 3 8 i - - bres bres regx, bit 3 8 i - - bset bset regx, bit 3 8 i - - btest btest regx, bit 3 7 i - - mtest mtest regx,const 3 7 i - - rlc rlc regx 2 7 i - i arithmetic instructions (continued)
st52f510/f513/f514 66/137 rol rol regx 2 7 i - i ror ror regx 2 7 i i - rrs rrs regx 2 7 i i - jump instructions mnemonic instruction bytes cycles z s c call call addr 3 11 - - - jp jp addr 3 6 - - - jpc jpc addr 3 5/6 - - - jpnc jpnc addr 3 5/6 - - - jpns jpns addr 3 5/6 - - - jpnz jpnz addr 3 5/6 - - - jps jps addr 3 5/6 - - - jpz jpz addr 3 5/6 - - - ret ret 1 8 - - - interrupt management instructions mnemonic instruction bytes cycles z s c halt halt 1 4/13 - - - megi megi 1 6/11 - - - mdgi mdgi 1 5 - - - reti reti 1 9 - - - rint rint int 2 6 - - - udgi udgi 1 5 - - - uegi uegi 1 6/11 - - - trap trap 1 9 - - - waiti waiti 1 7/10 - - - bitwise instructions (continued) control instructions mnemonic instruction bytes cycles z s c fuzzy fuzzy 1 4 - - - nop nop 1 6 - - - wdtrfr wdtrfr 1 6 - - - wdtslp wdtslp 1 5 - - -
st52f510/f513/f514 67/137 notes: regx, regy: register file address memx, memy: program/data memory addresses confx, confy: configuration registers addresses outx: output registers addresses inpx: input registers addresses const: constant value fuzzyx: fuzzy input registers i flag affected - flag not affected (*) the instruction blkset determines the start of a 32 byte block writing in flash or eeprom program/ data memory. during this phase (about 4 ms), the cpu is stopped to executing program instructions. the duration of the blkset instruction can be identified with this time.
st52f510/f513/f514 68/137 10 10-bit a/d converter 10.1 introduction st52f510/f513/f514 a/d converter is a 10-bit analog to digital converter with up to 8 analog inputs. the a/d converter offers a typical conversion time of 10 s in fast mode and of 20 s in slow mode. this period also includes the time of the integral sample and hold circuitry, which minimizes the need for external components and allows quick sampling of the signal for the minimum warping effect and integral conversion error. in addition the peripheral performs a calibration procedure in order to get the maximum precision allowed in the data of conversion. the calibration procedure is performed in two phases: the pre- charging phase and the tuning phase. the pre- charging process can be executed, after the peripheral start, to set-up the internal references and to speed-up the tuning process. the tuning process is carried-out during the channels conversion. note: the user must be take in account both the pre-charging time and some dummy conversion (at least 20) for the tuning before starting the data acquisition. it is recommended to repeat this procedure at the start-up and after a long time peripheral stop. figure 10.1 a/d converter structure the pre-charging process starts by starting the peripheral by setting to 1 the str bit of the ad_cr configuration register. to speed-up the calibration procedure, the pre-charging phase can be skipped when not necessary (for example when consecutive single conversions are performed). the user can disable the pre-charging by setting the prech bit in the ad_cr configuration register. the a/d peripheral converts the input voltage with a process of successive approximations using a fixed clock frequency derived from the 10 mhz internal oscillator, divided by a factor that depends on the speed mode: about 1.6 mhz in fast mode and 800 khz in slow mode. the speed mode is chosen by the sck bit of the ad_cr configuration register. the conversion range is found between the analog v ss and the a/d v ref references. the v ref can be either internal, derived from the v dd , or external by using the vref pin. the external reference voltage allows the application of more precise and stable reference voltages. the two modes are selected by using the ref bit of the ad_cr configuration register. remark: the voltage applied to the vref pin must be in the range 2.7v - v dd . the external reference voltage v ref is applied to the analog pin pb0. this pin shares the alternate functions with the first analog channel ain0: if the configuration registers control logic analog mux ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 vref vdd auto-zero / auto-calibration comparator successive approximation register sample & hold dac resistive reference ladder msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb status register input registers v ref successive approximation a/d converter int1 ref ch0 ch1 ch2 : 6 : 12 internal oscillator 10 mhz a/d clock sck seq pow str cont int0 resol prech
st52f510/f513/f514 69/137 external reference mode is chosen the ain0 channel is not used and the first channel of the conversion sequence becomes ain1. the converter uses a fully differential analog input configuration for a better noise immunity and precision performances. up to 8 multiplexed analog inputs are available. a single signal or a group of signals can be converted sequentially by simply programming the starting address of the last analog channel to be converted. single or continuous conversion modes are available. the result of the conversion of each a/d channel is stored in the 8-bit input register pairs (addresses from 41 to 56 (029h-038h)) according to the 8-bit or 10-bit mode. the resolution of conversion (8 or 10 bit) can be chosen by programming the resol bit of the ad_cr configuration register. in 8-bit mode the eight most significative bits (9:2) of the result of conversion is stored in the least significative byte of the register pair and the most significative is put to zero. in 10-bit mode the two most significative bits (9:8) are stored in the most significative byte of the register pair; the other bits (7:0) are stored in the least significative byte. in 10-bit mode the result of the conversion must be read in two steps: the msb and the lsb. the peripheral has been designed to avoid the side effects that can occur when the register are modified between the reading of the two bytes. in fact the latching of the input register pair is disabled after the reading of the first byte and it is enabled again after the reading of the second byte. user should pay attention to complete the two readings to guarantee the data of the conversion to be latched. when the converted signal is higher than v ref , an overflow occurs. in this case the 8/10 bits result are all set to 1 and the a/d overflow register bit (address 39 027h) corresponding to the channel is set to 1. the bit is reset at the next conversion having no overflow occurrence. st52f510/f513/f514 interrupt unit provides one maskable channel for the end of conversion and for the overflow control. it is possible to set the interrupt source on eoc or on overflow or on both by programming the int0 and int1 bits in the ad_cr configuration registers. note: the a/d converter interrupts are not enabled unless the bit 0 (mskad) of the configuration register 0 (int_mask) is enabled (set to 1). a power-down programmable bit (pow) allows the a/d converter to be set to a minimum consumption idle status. a stabilization time is required, after the power on, before accurate conversions can be performed. 10.2 functional description the conversion is monotonic, meaning that the result never decreases if the analog input doesn ? t and never increases if the analog input doesn ? t. if input voltage is less than vss (voltage supply low) then the result is equal to 00h. the a/d converter is linear and the digital result of the conversion is provided by the following formula: where reference voltage is v ref - v ss and n is 8 or 10 according with the conversion mode used. the accuracy of the conversion is described in the electrical characteristics section of the device datasheets. the a/d converter is not affected by the wait mode. when the icu enters halt mode with the a/d converter enabled, the converter is disabled until halt mode is exited and the start-up delay has elapsed. 10.3 operating modes four main operating modes can be selected by setting the values of the cont and seq bit in the a/d configuration register ad_cr. 10.3.1 one channel single mode. in this mode (cont=0, seq=0), the a/d provides an eoc signal after the end of the conversion of the specified channel; then the a/d waits for a new start event. the channel is identified by the bits ch2-ch0 in the configuration register ad_cr, while the bit str is used to command the start/ stop. 10.3.2 multiple channels single mode. in this mode (cont=0, seq=1) the a/d provides an eoc signal after the end of the channels sequence conversion identified by the three ad_cr configuration register bits ch2-0; then a/d waits for a new start event. 10.3.3 one channel continuous mode. in this mode (cont=1, seq=0) a continuous conversion flow is entered by a start event on the selected channel. at the end of each conversion, the relative input register is updated with the last conversion result, while the former value is lost. the conversion continues until a stop command is executed by writing a ? 0 ? in the apposite ad_cr configuration register bit str. digitalresult 2 n 1 ? () in putvoltage referencevoltage ------------------------------------------------------------ =
st52f510/f513/f514 70/137 10.3.4 multiple channels continuous mode. in this mode (cont=1, seq=1) a continuous conversion flow is entered by a start event on the selected channel sequence. the ch2-0 bits indicate the last channel of the sequence. at the end of each conversion the relative input registers are updated with the last conversion results, while the former values are lost. the conversion continues until a stop command is executed by writing a ? 0 ? in the apposite ad_cr configuration register bit str. 10.4 power down mode before enabling any a/d operation modes, set the power on bit (pow) of the configuration register ad_cr to ? 1 ? and then start the a/d converter by setting the str bit. it is suggested to execute the pre-charging after the power on to speed-up the auto calibration process. clearing the power on bit is useful when the a/d is not used, reducing the total chip power consumption. this state is also the reset configuration and it is forced by hardware when the core is in halt state (after a halt instruction execution). 10.5 a/d converter register description the following registers are related to the use of the a/d converter. 10.5.1 a/d converter configuration registers. a/d converter control register 1 (ad_cr1) configuration register 8 (08h) read/write reset value: 0000 0000 (00h) bit 7-5: ch2-ch0 channel number the number specified identifies the number of channels to be converted (multiple channel mode) or the channel to be converted (one channel mode) bit 4: sck a/d speed mode 0: slow mode (800 khz) 1: fast mode (1600 khz) bit 3: seq one/multiple channel mode 0: one channel mode 1: multiple channel mode bit 2: pow a/d converter power down/up 0: power down 1: power up bit 1: cont single/continuous mode 0: single mode 1: continuous mode bit 0: str a/d converter start bit 0: a/d converter stopped 1: a/d converter started a/d converter control register 2 (ad_cr2) configuration register 47 (02fh) read/write reset value: 0000 0000 (00h) bit 7-5: not used bit 4: prech pre-charging process on/off 0: pre-charge on (default) 1: pre-charge off bit 3: ref voltage reference (vref) source 0: internal from vdd 1: external from vref pin bit 2: resol 8/10 bits resolution 0: 10 bits 1: 8 bits bit 1: int1 overflow interrupt mask 0: interrupt disabled 1: interrupt enabled (if mskad=1) bit 0: int0 end of conversion interrupt mask 0: interrupt disabled 1: interrupt enabled (if mskad=1) 70 ch2 ch1 ch0 sck seq pow cont str 70 - - - prech ref resol int1 int0
st52f510/f513/f514 71/137 10.5.2 input registers. a/d converter overflow register (ad_ovf) input register 39 (027h) read only reset value: 0000 0000 (00h) bit 7-0: ovf7-ovf0 overflow flag 0: no overflow occurred in the last conversion 1: overflow occurred in the last conversion a/d converter data registers the converted digital values of the analog level applied to ain0-7 pins, are buffered in the following register couples: a/d channel 0 data msb (chan0_h) input register 41 (029h) read only reset value: 0000 0000 (00h) a/d channel 0 data lsb (chan0_l) input register 42 (02ah) read only reset value: 0000 0000 (00h) a/d channel 1 data msb (chan1_h) input register 43 (02bh) read only reset value: 0000 0000 (00h) a/d channel 1 data lsb (chan1_l) input register 44 (02ch) read only reset value: 0000 0000 (00h) a/d channel 2 data msb (chan2_h) input register 45 (02dh) read only reset value: 0000 0000 (00h) a/d channel 2 data lsb (chan2_l) input register 46 (02eh) read only reset value: 0000 0000 (00h) a/d channel 3 data msb (chan3_h) input register 47 (02fh) read only reset value: 0000 0000 (00h) a/d channel 3 data lsb (chan3_l) input register 48 (030h) read only reset value: 0000 0000 (00h) a/d channel 4 data msb (chan4_h) input register 49 (031h) read only reset value: 0000 0000 (00h) a/d channel 4 data lsb (chan4_l) input register 50 (032h) read only reset value: 0000 0000 (00h) a/d channel 5 data msb (chan5_h) input register 51 (033h) read only reset value: 0000 0000 (00h) a/d channel 5 data lsb (chan5_l) input register 52 (034h) read only reset value: 0000 0000 (00h) a/d channel 6 data msb (chan6_h) input register 53 (035h) read only reset value: 0000 0000 (00h) a/d channel 6 data lsb (chan6_l) input register 54 (036h) read only reset value: 0000 0000 (00h) a/d channel 7 data msb (chan7_h) input register 55 (037h) read only reset value: 0000 0000 (00h) a/d channel 7 data lsb (chan7_l) input register 56 (038h) read only reset value: 0000 0000 (00h) 70 ovf7 ovf6 ovf5 ovf4 ovf3 ovf2 ovf1 ovf0
st52f510/f513/f514 72/137 11 watchdog timer 11.1 functional description the watchdog timer (wdt) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. the wdt circuit generates an icu reset on expiry of a programmed time period, unless the program refreshes the wdt before the end of the programmed time delay. sixteen different delays can be selected by using the wdt configuration register. after the end of the delay programmed by the configuration register, if the wdt is active, it starts a reset cycle pulling the reset signal low. once the wdt is activated, the application program has to refresh the counter (by the wdtrfr instruction) during normal operation in order to prevent an icu reset. in st52f510/f513/f514 devices it is possible to choose between ? hardware ? or ? software ? watchdog. the hardware wdt allows the counting to avoid unwanted stops for external interferences. the first mode is always enabled unless the option byte 4 (wdt_en) is written with a special code (10101010b): only this code can switch the wdt in ? software ? mode, the other 255 possibilities keep the ? hardware ? mode enabled. the wdt is started and refreshed by using the wdtrfr instruction. when the software mode is enabled, the wdtslp instruction stops the wdt avoiding timeout resets. when the wdt is in hardware mode, neither the wdtslp instruction nor external interference can stop the counting. the ? hardware ? wdt is always enabled after a reset. figure 11.1 watchdog block diagram the working frequency of wdt (pres clk in the figure 11.1 ) is equal to the clock master. the clock master is divided by 500, obtaining the wdt clk signal that is used to fix the timeout of the wdt. according to the wdt_cr configuration register values, a wdt delay between 0.1ms and 937.5ms can be defined when the clock master is 5 mhz. by changing the clock master frequency the timeout delay can be calculated according to the configuration register values. the first 4 bits of the wdt_cr register are used, obtaining 16 different delays. 11.2 register description sw watchdog enable (wdt_en) option byte 4 (04h) bit 7-0: wdten7-0 sw watchdog enable byte writing the code 10101010 in this byte the software watchdog mode is enabled. d0 d1 d2 d3 configuration register reset wdtrfr pres clk = clk master wdtslp prescaler wdt reset generator reset wtd clk table 11.1 watchdog timing range (5 mhz) wdt timeout period (ms) min 0.1 max 937.5 70 wdten7 wdten6 wdten5 wdten4 wdten3 wdten2 wdten1 wdten0
st52f510/f513/f514 73/137 watchdog control register (wdt_cr) configuration register 7 (07h) read/write reset value: 0000 0001 (01h) bit 7-4: not used bit 3-0: d3-0 watchdog clock divisor factor bits the watchdog clock (wdt clk) is divided by the numeric factor determined by these bits, according with table 11.2 and the following formula: 70 ----d3d2d1d0 timeout ms () 510 5 divisionfactor clock mhz () ----------------------------------------------------------------- = table 11.2 watchdog timeout configuration examples wdt_cr(3:0) division factor timeout values (ms) 5 mhz 10 mhz 20mhz 0000 1 0.1 0.05 0.025 0001 625 62.5 31.25 15.625 0010 1250 125 62.5 31.25 0011 1875 187.5 93.75 46.875 0100 2500 250 125 62.5 0101 3125 312.5 156.25 78.125 0110 3750 375 187.5 93.75 0111 4375 437.5 218.75 109.375 1000 5000 500 250 125 1001 5625 562.5 281.25 140.625 1010 6250 625 312.5 156.25 1011 6875 687.5 343.75 171.875 1100 7500 750 375 187.5 1101 8125 812.5 406.25 203.125 1110 8750 875 437.5 218.75 1111 9375 937.5 468.75 234.375
st52f510/f513/f514 74/137 12 pwm/timers 12.1 introduction st52f510/513/514 offers two on-chip pwm/timer peripherals. all st52f510/513/514 pwm/timers have the same internal structure. the timer consists of a 16-bit counter with a 16-bit programmable prescaler, giving a maximum count of 2 32 (see figure 12.1 ). each timer has two different working modes, which can be selected by setting the correspondent bit txmod of the pwmx_cr1 conf. register: timer mode and pwm (pulse width modulation) mode. all the timers have autoreload functions; in pwm mode the reload value can be set by the user. each timer output is available on the apposite external pins configured in alternate function and in one of the output modes. pwm/timer 0 can also use external start/stop signals in order to perform input capture and output compare, external reset signal, and external clock to count external events: tstrt, tres and tclk pins. in addition, the start/ stop and reset signals have configurable polarity (falling or rising edge). remark: to use tres, tstrt, tclk external signals the related pins must be configured in alternate function and in one of input modes. for each timer, the contents of the 16-bit counter are incremented on the rising edge of the 16-bit prescaler output (prescout) and they can be read at any instant of the counting phase by accessing the input registers pwmx_count_in_x; the value is stored in two 8- bit registers (msb and lsb) for each pwm/timer. the input registers couple pwmx_capture_x store the counter value after the last stop signal (only timer mode). the counter value is not stored after a reset signal. figure 12.1 pwm/timer counter block diagram warning: both of the pwmx_count_in_x registers must be always read. to avoid side effects, the values stored inside these registers are frozen, and new updates cannot be stored, until both the values are read. the peripheral status can also be read from the input registers pwmx_status. these registers report start/stop, set/reset status, txout signal and the counter overflow flag. this last signal is set after the first eoc and it is reset by a timer reset (internal or external). 12.2 timer mode timer mode is selected writing 0 in the txmod bit. each timer requires three signals: timer clock (tmrclkx), timer reset (txres) and timer start (txstrt) (see figure 12.1 ). each of these signals can be generated internally, and/or externally only for timer 0, by using tres, tstrt and tclk pins. the prescaler output (prescout) increments the counter value on the rising edge. prescout is obtained from the internal clock signal (clkm) or, only for timer0, from the external signal provided on the apposite pin. note: the external clock signal applied on the tclk pin must have a frequency that is at least two times smaller than the internal master clock. the prescaler output period can be selected by setting the txpresc bits with one of the 17 division factors available. tmrclk frequency is divided by a factor equal to the power of two of the prescaler values (up to 2 16 ). txres resets the content of the 16-bit counter to zero. it is generated by writing 0 in the txres bit of the pwmx_cr1 configuration register and/or it can be driven by the tres pin if configured (only timer0). bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 14 bit 15 bit 3 bit 0 bit 1 bit 2 bit 4 bit 5 17 - 1 multiplexer 16-bit prescaler 16-bit counter prescx tmrclkx prescout txres txstrt bit 14 bit 15
st52f510/f513/f514 75/137 figure 12.2 timer 0 external start/stop mode txstrt signal starts/stops the timer from counting only if the peripherals are configured in timer mode. the timers are started by writing 1 in the txstrt bit of the pwmx_cr1 and are stopped by writing 0. this signal can be generated internally and/or externally by forcing the tstrt pin (only timer0). timer 0 start/stop can be given externally on the tstrt pin. in this case, the t0strt signal allows the user to work in two different configurable modes (see figure 12.2 ): level (time counter): if the t0strt signal is high, the timer starts counting. when the t0strt is low the timer stops counting and the 16-bit current value is stored in the pwm0_count_in_x input registers couple. edge (period counter): after reset, on the first t0strt rising edge, timer 0 starts counting and at the next rising edge it stops. in this manner the period of an external signal may be measured. the same above mentioned modes, can be used to reset the timer0 by using the tres pin signal. the polarity of the t0srtr start/stop signal can be changed by setting the strpol and respol bits in the int_pol configuration register (01h bit 3 and 4). when these bits are set, the pwm/timer 0 is started/set on the low level or in the falling edge of the signal applied in the pins. the timer output signal, txout, is a signal with a frequency equal to the one of the 16 bit-prescaler output signal, prescoutx, divided by a 16-bit counter set by writing the output register couple pwmx_count_out_x. note: the contents of these registers upgrades the timer counter after it stops counting. since the register couple is written in two steps this can cause side effects. in order to avoid this, the user should write the msb before writing the lsb: actually, the 16-bit value is latched in parallel when the lsb is written. by writing only the lsb (and msb equal to 0), the pwm/timer is used as an 8 bit counter. warning: in timer mode the reload register couple pwmx_reload_x (see pwm mode) must be set to the higher value ffffh (65535) otherwise it can affect the count duration. there can be two types of txout waveforms: type 1: txout waveform equal to a square wave with a 50% duty-cycle type 2: txout waveform equal to a pulse signal with the pulse duration equal to the prescaler output signal. figure 12.3 txout signal types level edge start stop start start stop start 01 1 0 4 4 3 2 reset clock counted value timer output type 1 type 2 prescout*counter
st52f510/f513/f514 76/137 figure 12.4 pwm mode with reload 12.3 pwm mode the pwm working mode for each timer is obtained by setting the txmod bit of the configuration register pwmx_cr1. the txout signal in pwm mode consists of a signal with a fixed period, whose duty cycle can be modified by the user. the txout period is fixed by setting the 16-bit prescaler bits (txpresc) in the pwmx_cr2 and the 16-bit reload value by writing the relative output registers couple pwmx_reload_x. the 16-bit prescaler divides the master clock clkm by powers of two, determining the maximum length period. reload determines the maximum value that the counter can count before starting a new period. the use of the two 16-bit values allows the txout period to be set with more precision when needed. by decreasing the reload value the counting resolution decreases. in order to obtain the maximum resolution, reload value should be set to 0ffffh and the period corresponds to the one established by the prescaler value. the value set in the 16-bit counter by writing the counter output registers couple, determines the duty-cycle: when count reaches the counter value the txout signal changes from high to low level. the period of the pwm signal is obtained by using the following formula: t=pwmx - reload * 2 txpresc *tmrclkx where txpresc equals the value set in the txpresc bits of the pwmx_cr2 configuration register and tmrclkx is the period of the timer clock that drives the prescaler. the duty cycle of the pwm signal is obtained by the following formula: note: the pwm_x_count value must be lower than or equal to the pwm_x_reload value. when it is equal, the txout signal is always at high level. if the output register pwm_x_count is 0, txout signal is always at a low level. by using a 20 mhz clock a pwm frequency that is close to 305 khz can be obtained with a reload equal to ffffh and the prescaler set to 0000h. the timer0 clock clkm can also be supplied with an external signal, applied on the tclk pin, which must have a frequency that is at least two times smaller than the internal master clock. note: the timers have to complete the previous counting phase before using a new value of the counter. if the counter value is changed during counting, the new values of the timer counter are only used at the end of the previous counting phase. the counter buffer is written in two steps (one byte per time) and is latched only after the lsb is written. in order to avoid side effects, the user should write the msb before writing the lsb. by only writing the lsb, the pwm/timer is used as an 8 bit counter. the same mechanism is applied to the two bytes of reload but, differently of the counter it is set immediately. nevertheless, it is recommended that the reload value be written when the timer is stopped in order to avoid incongruence with the counter value. the same recommendation is made when reading the two bytes of the counter: it is performed in two steps, so if the timer is running, the carry of the lsb to the msb can cause the wrong 16-bit value reading. a reload value greater than 1 must always be used. t t 65535 reload value counter value 0 pwm output ton t d cycle t on t -------- pwmxcount pwmxreload ------------------------------------------ ==
st52f510/f513/f514 77/137 when the timers are in reset status, or when the device is reset, the txout pins goes in threestate. if these outputs are used to drive external devices, it is recommended that the related pins be left in the default configuration (input threestate) or change them in this configuration. in pwm mode the pwm/timers can only be set or reset: start/stop signals do not affect the timers. txres resets the content of the 16-bit counter to zero. it is generated by writing 0 in the corresponding txres bit of the pwmx_cr1 configuration register and/or it can be driven by the tres pin if it is configured (only timer0). 12.3.1 simultaneous start. the pwm/timers can be started simultaneously. the t0sync and t1sync bits in pwm0_cr3 configuration registers mask the reset of each timer. after enabling each single pwm/timer, they are started by putting off the mask with a single writing in the pwm0_cr3 register. the timers start counting simultaneously, but the output pulses are generated according to the modality configured (square or pulse mode). 12.4 timer interrupts the pwm/timer can be programmed to generate an interrupt request, both on the falling and the rising of the txout signal and when there ? s a stop signal (external or internal). by using the txies, txier and txief bits of the configuration registers pwmx_cr1, the interrupt sources can be switched on/off. all the interrupt sources may be activated at the same time: sources can be distinguished by reading the pwmx_status input register. the interrupt on the falling edge corresponds to half of a counting period in timer mode when the waveform is set to square wave and to the end of the ton phase in pwm mode. note: when the pwm counter is set to 0 or 65535, the interrupt occurs at the end of each control period. in order to be active, the pwm/timers interrupts must be enabled by writing the interrupt mask register (int_mask) in the configuration register space, bits mskt0 and mskt1. 12.5 pwm/timer 0 register description the following registers are related to the use of the pwm/timer 0. 12.5.1 pwm/timer 0 configuration registers. pwm/timer 0 control register 1 (pwm0_cr1) configuration register 9 (09h) read/write reset value: 0000 0000 (00h) bit 7: t0mod pwm/timer 0 mode 0: timer mode 1: pwm mode bit 6: t0ies interrupt on stop signal enable 0: interrupt disabled 1: interrupt enabled bit 5: t0ief interrupt on t0out falling enable 0: interrupt disabled 1: interrupt enabled bit 4: t0ier interrupt on t0out rising enable 0: interrupt disabled 1: interrupt enabled bit 3: strmod start signal mode 0: start/stop on level 1: start/stop on edge bit 2: t0strt pwm/timer 0 start bit 0: timer 0 stopped 1: timer 0 started bit 1: resmod reset signal mode 0: set/reset on level 1: set/reset on edge bit 0: t0res pwm/timer 0 reset bit 0: pwm/timer 0 reset 1: pwm/timer 0 set 70 t0mod t0ies t0ief t0ier strmod t0strt resmod t0res
st52f510/f513/f514 78/137 pwm/timer 0 control register 2 (pwm0_cr2) configuration register 10 (0ah) read/write reset value: 0000 0000 (00h) bit 7-6: not used bit 5: t0wav t0out waveform 0: pulse (type2) 1: square (type1) bit 4-0: t0presc pwm/timer 0 prescaler the pwm/timer 0 clock is divided by a factor equal to 2 t0presc . the maximum value allowed for t0presc is 10000 (010h) . pwm/timer 0 control register 3 (pwm0_cr3) configuration register 11 (0bh) read/write reset value: 0000 0000 (00h) bit 7: t1sync pwm/timer 1 set/reset mask 0: set/reset activated 1: set/reset masked bit 6: not used bit 5: t0sync pwm/timer 0 set/reset mask 0: set/reset activated 1: set/reset masked bit 4: t0cks pwm/timer 0 clock source 0: internal clock 1: external clock from tclk bit 3-2: strsrc pwm/timer 0 start signal source 00: internal from t0strt bit 01: external from tstrt pin 10: both internal and external bit 1-0: ressrc pwm/timer 0 reset source 00: internal from t0res bit 01: external from tres pin 10: both internal and external interrupt polarity register (int_pol) configuration register 1 (01h) read/write reset value: 0000 0000 (00h) bit 7-5: not used bit 4: respol reset signal polarity 0: set/reset on low level/rising edge 1: set/reset on high level/falling edge bit 3: strpol start signal polarity 0: start on high level/rising edge 1: start on low level/falling edge bit 2-0: see interrupt registers description 12.5.2 pwm/timer 0 input registers. pwm/timer 0 counter high input register (pwm0_count_in_h) input register 21 (015h) read only reset value: 0000 0000 (00h) bit 7-0: t0ci15-8 pwm/timer 0 counter msb in this register the current value of the timer 0 counter msb can be read. warning: both of the pwmx_count_in_x registers must be always read. to avoid side effects, the values stored inside these registers are frozen, and new updates cannot be stored, until both the values are read. 74 0 - - t0wav t0presc 7420 t1sync - t0sync t0cks strsrc ressrc 70 - - - respol strpol polpb polpa polnmi 70 t0ci15 t0ci14 t0ci13 t0ci12 t0ci11 t0ci10 t0ci9 t0ci8
st52f510/f513/f514 79/137 pwm/timer 0 counter low input register (pwm0_count_in_l) input register 22 (016h) read only reset value: 0000 0000 (00h) bit 7-0: t0ci7-0 pwm/timer 0 counter lsb in this register the current value of the timer 0 counter lsb can be read. warning: both of the pwmx_count_in_x registers must be always read. to avoid side effects, the values stored inside these registers are frozen, and new updates cannot be stored, until both the values are read. pwm/timer 0 status register (pwm0_status) input register 23 (017h) read only reset value: 0000 0000 (00h) bit 7-4: not used bit 3: t0ovfl pwm / timer 0 counter overflow flag 0: no overflow occurred since last reset 1: overflow occurred bit 2: t0out t0out pin value 0: t0out pin is at logical level 0 1: t0out pin is at logical level 1 bit 1: t0rst reset status 0: pwm/timer 0 is reset 1: pwm/timer 0 is set bit 0: t0sst start status 0: pwm/timer 0 is stopped 1: pwm/timer 0 is running pwm/timer 0 capture high input register (pwm0_capture_h) input register 24 (018h) read only reset value: 0000 0000 (00h) bit 7-0: t0cp15-8 pwm/timer 0 capture msb in this register the counter value after the last stop can be read. pwm/timer 0 capture low input register (pwm0_capture_l) input register 25 (019h) read only reset value: 0000 0000 (00h) bit 7-0: t0cp7-0 pwm/timer 0 capture lsb in this register the counter value after the last stop can be read. 12.5.3 pwm/timer 0 output registers. pwm/timer 0 counter high output register (pwm0_count_out_h) output register 7 (07h) write only reset value: 0000 0000 (00h) bit 7-0: t0co15-8 pwm/timer 0 counter msb this register is used to write the timer 0 counter value (msb). note: this register is latched after writing the lsb part (pwm_count_out_l: see below). for this reason this register must be written before the lsb. 70 t0ci7 t0ci6 t0ci5 t0ci4 t0ci3 t0ci2 t0ci1 t0ci0 70 - - - - t0ovfl t0out t0rst t0sst 70 t0cp15 t0cp14 t0cp13 t0cp12 t0cp11 t0cp10 t0cp9 t0cp8 70 t0cp7 t0cp6 t0cp5 t0cp4 t0cp3 t0cp2 t0cp1 t0cp0 70 t0co15 t0co14 t0co13 t0co12 t0co11 t0co10 t0co9 t0co8
st52f510/f513/f514 80/137 pwm/timer 0 counter low output register (pwm0_count_out_l) output register 8 (08h) write only reset value: 0000 0000 (00h) bit 7-0: t0co7-0 pwm/timer 0 counter lsb this register is used to write the timer 0 counter value (lsb). note: writing this register, the pwm0_count_out_x couple is latched in the internal registers of the peripherals. for this reason, this register should be written after the msb one. pwm/timer 0 reload high output register (pwm0_reload_h) output register 9 (09h) write only reset value: 1111 1111 (0ffh) bit 7-0: t0rel15-8 pwm/timer 0 reload msb this register is used to write the timer 0 reload value (msb). note: this register is latched after writing the lsb part (pwm0_reload_l: see below). for this reason, this register must be written before the lsb. pwm/timer 0 reload low output register (pwm0_reload_l) output register 10 (0ah) write only reset value: 1111 1111 (0ffh) bit 7-0: t0rel7-0 pwm/timer 0 reload lsb this register is used to write the timer 0 reload value (lsb). note: by writing this register, the pwm0_reload_x couple is latched in the internal registers of the peripherals. for this reason this register should be written after the msb one. 12.6 pwm/timer 1 register description the following registers are related to the use of the pwm/timer 1. 12.6.1 pwm/timer 1 configuration registers. pwm/timer 1 control register 1 (pwm1_cr1) configuration register 12 (0ch) read/write reset value: 0000 0000 (00h) bit 7: t1mod pwm/timer 1 mode 0: timer mode 1: pwm mode bit 6: t1ies interrupt on stop signal enable 0: interrupt disabled 1: interrupt enabled bit 5: t1ief interrupt on t1out falling enable 0: interrupt disabled 1: interrupt enabled bit 4: t1ier interrupt on t1out rising enable 0: interrupt disabled 1: interrupt enabled bit 3: not used: it must be left at reset status bit 2: t1strt pwm/timer 1 start bit 0: timer 1 stopped 1: timer 1 started bit 1: not used: it must be left at reset status bit 0: t1res pwm/timer 1 reset bit 0: pwm/timer 1 reset 1: pwm/timer 1 set 70 t0co7 t0co6 t0co5 t0co4 t0co3 t0co2 t0co1 t0co0 70 t0rel15 t0rel14 t0rel13 t0rel12 t0rel11 t0rel10 t0rel9 t0rel8 70 t0rel7 t0rel6 t0rel5 t0rel4 t0rel3 t0rel2 t0rel1 t0rel0 70 t1mod t1ies t1ief t1ier - t1strt - t1res
st52f510/f513/f514 81/137 pwm/timer 1 control register 2 (pwm1_cr2) configuration register 13 (0dh) read/write reset value: 0000 0000 (00h) bit 7-6: not used bit 5: t1wav t1out waveform 0: pulse (type2) 1: square (type1) bit 4-0: t1presc pwm/timer 1 prescaler the pwm/timer 1 clock is divided by a factor equal to 2 t1presc . the maximum value allowed for t1presc is 10000 (010h) . 12.6.2 pwm/timer 1 input registers. pwm/timer 1 counter high input register (pwm1_count_in_h) input register 26 (01ah) read only reset value: 0000 0000 (00h) bit 7-0: t1ci15-8 pwm/timer 1 counter msb in this register the current value of the timer 1 counter msb can be read. warning: both of the pwmx_count_in_x registers must be always read. to avoid side effects, the values stored inside these registers are frozen, and new updates cannot be stored, until both the values are read. pwm/timer 1 counter low input register (pwm1_count_in_l) input register 27 (01bh) read only reset value: 0000 0000 (00h) bit 7-0: t1ci7-0 pwm/timer 1 counter lsb in this register the current value of the timer 1 counter lsb can be read. warning: both of the pwmx_count_in_x registers must be always read. to avoid side effects, the values stored inside these registers are frozen, and new updates cannot be stored, until both the values are read. pwm/timer 1 status register (pwm1_status) input register 28 (01ch) read only reset value: 0000 0000 (00h) bit 7-4: not used bit 3: t1ovfl pwm / timer 1 counter overflow flag 0: no overflow occurred since last reset 1: overflow occurred bit 2: t1out t1out pin value 0: t1out pin is at logical level 0 1: t1out pin is at logical level 1 bit 1: t1rst reset status 0: pwm/timer 1 is reset 1: pwm/timer 1 is set bit 0: t1sst start status 0: pwm/timer 1 is stopped 1: pwm/timer 1 is running pwm/timer 1 capture high input register (pwm1_capture_h) input register 29 (01dh) read only reset value: 0000 0000 (00h) bit 7-0: t1cp15-8 pwm/timer 1 capture msb in this register the counter value after the last stop can be read. 75 0 - - t1wav t1presc 70 t1ci15 t1ci14 t1ci13 t1ci12 t1ci11 t1ci10 t1ci9 t1ci8 70 t1ci7 t1ci6 t1ci5 t1ci4 t1ci3 t1ci2 t1ci1 t1ci0 70 - - - - t1ovfl t1out t1rst t1sst 70 t1cp15 t1cp14 t1cp13 t1cp12 t1cp11 t1cp10 t1cp9 t1cp8
st52f510/f513/f514 82/137 pwm/timer 1 capture low input register (pwm1_capture_l) input register 30 (01eh) read only reset value: 0000 0000 (00h) bit 7-0: t1cp7-0 pwm/timer 1 capture lsb in this register the counter value after the last stop can be read. 12.6.3 pwm/timer 1 output registers. pwm/timer 1 counter high output register (pwm1_count_out_h) output register 11 (0bh) write only reset value: 0000 0000 (00h) bit 7-0: t1co15-8 pwm/timer 1 counter msb this register is used to write the timer 1 counter value (msb). note: this register is latched after writing the lsb part (pwm1_count_out_l: see below). for this reason, this register must be written before the lsb. pwm/timer 1 counter low output register (pwm1_count_out_l) output register 12 (0ch) write only reset value: 0000 0000 (00h) bit 7-0: t1co7-0 pwm/timer 1 counter lsb this register is used to write the timer 1 counter value (lsb). note: by writing this register, the pwm1_count_out_x couple is latched in the internal registers of the peripherals. for this reason this register should be written after the msb one. pwm/timer 1 reload high output register (pwm1_reload_h) output register 13 (0dh) write only reset value: 1111 1111 (0ffh) bit 7-0: t1rel15-8 pwm/timer 1 reload msb this register is used to write the timer 1 reload value (msb). note: this register is latched after writing the lsb part (pwm1_reload_l: see below). for this reason, this register must be written before the lsb. pwm/timer 1 reload low output register (pwm0_reload_l) output register 14 (0eh) write only reset value: 1111 1111 (0ffh) bit 7-0: t1rel7-0 pwm/timer 1 reload lsb this register is used to write the timer 1 reload value (lsb). note: by writing this register, the pwm1_reload_x couple is latched in the internal registers of the peripherals. for this reason, this register should be written after the msb one. 70 t1cp7 t1cp6 t1cp5 t1cp4 t1cp3 t1cp2 t1cp1 t1cp0 70 t1co15 t1co14 t1co13 t1co12 t1co11 t1co10 t1co9 t1co8 70 t1co7 t1co6 t1co5 t1co4 t1co3 t1co2 t1co1 t1co0 70 t1rel15 t1rel14 t1rel13 t1rel12 t1rel11 t1rel10 t1rel9 t1rel8 70 t1rel7 t1rel6 t1rel5 t1rel4 t1rel3 t1rel2 t1rel1 t01rel0
st52f510/f513/f514 83/137 13 serial communication interface the serial communication interface (sci) integrated into st52f510/f513/f514 provides a general purpose shift register peripheral, several widely distributed devices to be linked, through their sci subsystem. sci gives a serial interface providing communication with the speed from less than 300 up to over 115200 baud, and a flexible character format. sci is a full-duplex uart-type asynchronous system with standard non return to zero (nrz) format for the transmitted/received bit. the length of the transmitted word is 10/11 bits (1 start bit, 8/ 9 data bits, 1 stop bit). sci is composed of three modules: receiver, transmitter and baud-rate generator. 13.1 sci receiver block the sci receiver block manages the synchronization of the serial data stream and stores the data characters. the sci receiver is mainly composed of two sub-systems: recovery buffer block and scdr_rx block. sci receives data deriving from the rx pin and drives the recovery buffer block, which is a high- speed shift register operating at a clock frequency (clock_rx) 16 times higher than the fixed baud rate (clock_tx). this sampling rate, higher than the baud rate clock, detects the start condition, noise error and frame error. when the sci receiver is in idle status, it is waiting for the start condition, which is obtained with a logic level of 0, consecutive to a logic level 1. this condition is detected if, with the fixed sampling time, a logic level 0 is sampled after three logic levels of 1. the recognition of the start bit forces the sci receiver block to start a data acquisition sequence. the data acquisition sequence is configured by the apposite configuration register, allowing the following data frame formats (see figure 13.1 ): figure 13.1 sci transmitted word structures 8 bit length, 1 stop bit, no parity bit 8 bit length, 2 stop bit, no parity bit 8 bit length, 1 stop bit, with parity bit 9 bit length, 1 stop bit, no parity bit the parity bit (if used) can be configured for even or odd parity check. if the 9-bit length format is configured, this bit is used in transmission for the ninth bit (see below). the ninth bit received can be read in the r8 bit of the sci status register, address 37 (035h) bit 2 (see figure 13.3 ). figure 13.2 sci block diagram 7 6 5 432 10 8 9 7 6 5 43210 8 9 10 stop data start stop data start sci register file scdr_tx ldpr/ldpe/ldpi baud-rate generator ldri shift register scdr_rx recovery buffer rx tx sci transmitter sci receiver mclk program/data memory ir or
st52f510/f513/f514 84/137 recognition of a stop condition transfers data received from the recovery buffer to the scdr_rx buffer, adding the eventual ninth data bit. after this operation, rxf flag (bit 5) of sci status input register is set to logic level 1. the control unit reads data from the scdr_rx buffer (in read-only mode) by reading the sci_in input register (address 36 024h) with the ldri instruction and provides a reset at logic level 0 to the rxf flag. if data of the recovery buffer is ready to be transferred into the scdr_rx buffer, but the previous one has not been read by the core, an overrun error takes place: the sci status register flag overr (bit 4) indicates the error condition. in this case, information that is stored in the scdr_rx buffer is not altered, but the one that has caused the overrun error can be overwritten by new data deriving from the serial data line. 13.1.1 recovery buffer block . this block is structured as a synchronized finite state machine on the clock_rx signal. when the recovery buffer block is in idle state it waits for the reception of the correct 1 and 0 sequence representing start. recognition takes place by sampling the input rx at clock_rx frequency, which has a frequency that is 16 times higher than clock_tx. for this reason, while the external transmitter sends a single bit, the recovery buffer block samples 16 states (from sample1 to sample16). analysis of the rx input signal is carried out by checking three samples for each bit received. if these three samples are not equal, then the noise error flag, nserr (bit 7), of sci status register is set to 1 and the data received value will be the one assumed by the majority of the samples. the procedure described above, allows sci not to becomes idle, because of a limited noise due to an erroneous sampling, the transmission is recognized as correct and the noise flag error is set. at the end of the cycle of the reception of a bit, the recovery buffer block will repeat the same steps 9 times: one step for each bit received, plus one for the stop acquisition (10 times in case of 9-bit data, double stop or parity check). at the end of data reception the recovery buffer block will supply information about eventual frame errors by setting the 1 frerr flag (bit 6) of the sci status register to 1. a frame error can occur if the parity check hasn ? t been successfully achieved or if the stop bit has not been detected. if the recovery buffer block receives 10 consecutive bits at logic level 0, a line break condition occurs and the related interrupt request is sent. 13.1.2 scdr_rx block. it is a finite state machine synchronized with the clock master signal, fckm. the scdr_rx block waits for the signal of complete reception from the recovery buffer in order to load the word received. moreover, the scdr_rx block loads the values of frerr and nserr flag bits of the status register, and sets the rxf flag to 1. by using the ldri instruction data is transferred to register file and rxf flag is reset to 0, to indicate that the scdr_rx block is empty. if new data arrives before the previous one has been transferred to register file, the overrun error occurs and the overr flag of status register is set to 1. figure 13.3 sci status register d7 d6 d5 d4 d3 d2 d1 d0 sci_status input register 37 txend - end transmission txem - transmission data register empty r8 - received ninth bit nserr - noise error not used overr - overrun error rxf - receive data register full frerr - frame error
st52f510/f513/f514 85/137 13.2 sci transmitter block the sci transmitter block consists of the following blocks: scdr_tx and shift register, synchronized, respectively, with the clock master signal (fckm) and the clock_tx. the whole block receives the settings for the following transmission modes through the configuration register: 8 bit length, 1 stop bit, no parity bit 8 bit length, 2 stop bit, no parity bit 8 bit length, 1 stop bit, with parity bit 9 bit length, 1 stop bit, no parity bit in case of 9 bit frame transmission, the most significative bit arrives through the bit par/t8 (bit 2) of the sci_cr1 configuration register. in an 8- bit transmission, instead, this bit is used to configure the data format: in particular to choose the polarity control (even or odds) to implement the parity check (see above). after a reset, the scdr_tx block is in idle state until it receives an enabling signal by writing the txstrt bit of the sci_cr2 configuration register. the data is loaded on the peripheral register sci_out (address 23 017h) by using the instruction lppr, ldpi or ldpe. if the transmission is enabled (txtstrt bit of the sci_cr2 configuration register), the data to be transmitted is transferred from the output register to scdr_tx block and the txem flag (bit 1) of the sci status register is reset to 0 to indicate scdr_tx block is full. if the core supplies new data, this could not be loaded in the scdr_tx block until the current data has not been unloaded on the shift register block. meaning that only when txem is 1 data can be loaded in the scdr_tx block. when the shift register block loads the data to be transmitted on an internal buffer, the txend flag (bit 0) of the sci status register is reset to 0 to indicate the beginning of a new transmission. at the end of transmission txend is set to 1, allowing new data coming from scdr_tx to be loaded in the shift register. it is important to underline that txend = 1 does not mean scdr_tx is ready to receive a new data. for this reason, it is better to utilize the txem signal to synchronize the load instruction to the sci transmitter block if the txstrt bit is reset, the transmission is stopped, but the sci transmitter block completes the transmission in progress before resetting. 13.3 baud rate generator block the baud rate generator block performs the division of the clock master signal (fckm) in a set of synchronism frequencies for the serial bit reception/transmission on the external line. reception frequency (clock_rx) is 16 times higher than the transmission frequency (clock_tx). to adapt the baud rate generator to the clock master frequency supplied by the user, a 12-bit prescaler must be programmed by loading the configuration registers sci_cr2 (presc_h bit 11:8 of the 12 bit prescaler) and sci_cr3 (presc_l bit 7:0 of the 12 bit prescaler). the prescaler allows the programming of all standard baud rates by using the most common clock master sources. the prescaler value can be obtained by the following formula: where fckm is the clock master frequency (expressed in hz) and baud is the desired baud rate (expressed in bit/second). the obtained value is rounded to the nearest integer value. this rounding can cause an error in the obtained baud rate. this error must be lower than 3%. to verify that the presc value satisfies this constrain, the obtained baud rate must be computed by inverting the previous formula: then the following relation can be used to verify that the difference with the desired baud rate is lower than 3%: table 13.1 shows the recommended prescaler values for common clock master frequencies. to get more precision in baud rate, standard quartz frequencies for serial communication can be used. the corresponding prescaler values for these frequencies are showed in the table 13.2 . presc round ckm 16 baud ---------------------------- - ?? ?? = baud ckm 16 presc ------------------------------- = baud baud ? baud ------------------------------------------ - 0,03 <
st52f510/f513/f514 86/137 table 13.1 recommended prescaler values for common frequencies (baud/mhz) 145810121620 1200 52 208 260 417 521 625 833 1042 2400 26 104 130 208 260 313 417 521 4800 13 52 65 104 130 156 208 260 9600 - 2633526578104130 19200 - 13162633395265 38400 - - 8 1316202633 57600 - - - - 11 13 17 22 115200 -------11 table 13.2 recommended prescaler values for serial communication quartz (baud/mhz) 1.843 2.458 3.686 4.915 6.144 7.373 9.830 11.059 12.288 14.746 19.661 1200 96 128 192 256 320 384 512 576 640 768 1024 2400 48 64 96 128 160 192 256 288 320 384 512 4800 24 32 48 64 80 96 128 144 160 192 256 9600 12 16 24 32 40 48 64 72 80 96 128 19200 6 8 12 16 20 24 32 36 40 48 64 38400 3 4 6 8 10 12 16 18 20 384 32 57600 2 - 4 - - 8 - 12131621 115200 1-2- -4-6-8-
st52f510/f513/f514 87/137 13.4 sci register description the following registers are related to the use of the sci peripheral. 13.4.1 sci configuration registers. sci control register 1 ( sci_cr1 ) configuration register 22 (016h) read/write reset value: 0000 0000 (00h) bit 7: rxfint scdr_rx buffer full interrupt mask 0: interrupt disabled 1: interrupt enabled bit 6: ovrint overrun interrupt mask 0: interrupt disabled 1: interrupt enabled bit 5: brkint break interrupt mask 0: interrupt disabled 1: interrupt enabled bit 4: txemint scdr_tx buffer empty interrupt 0: interrupt disabled 1: interrupt enabled bit 3: txenint tx end interrupt mask 0: interrupt disabled 1: interrupt enabled bit 2: par/t8 parity type selection or tx 9th bit 0: parity odd if enabled, else tx 9th bit=0 1: parity even if enabled, else tx 9th bit=1 bit 1-0: frm frame type selection 00: 8 bit, no parity, 1 stop bit 01: 8 bit, no parity, 2 stop bit 10: 8 bit, parity, 1 stop bit 11: 9 bit, no parity, 1 stop bit note: the sci interrupts are not enabled unless the bit 3 (msksci) of the configuration register 0 (int_mask) is enabled (set to 1). sci control register 2 ( sci_cr2 ) configuration register 23 (017h) read/write reset value: 0000 0000 (00h) bit 7-4: presc_h baud rate prescaler (bit 11:8) these bits are the higher part of the prescaler (see sci_cr3 configuration register) which determinates the baud rate of the communication, according to table 13.1 and table 13.2 , as explained in paragraph 13.3 . bit 3-2: not used bit 1: rxstrt reception enable 0: rx disabled 1: rx enabled bit 0: txstrt transmission enable 0: tx disabled 1: tx enabled sci control register 3 ( sci_cr3 ) configuration register 43 (02bh) read/write reset value: 0000 0000 (00h) bit 7-0: presc_l baud rate prescaler (bit 7:0) these bits are the lower part of the prescaler (see sci_cr2 configuration register) which determinates the baud rate of the communication, according to table 13.1 and table 13.2 , as explained in paragraph 13.3 . 720 rxfint ovrint brkint txemint txenint par/t8 frm 7420 presc_h - rxstrt txstrt 70 presc_l
st52f510/f513/f514 88/137 13.4.2 sci input registers. sci rx data input register (sci_in) input register 36 (024h) read only reset value: 0000 0000 (00h) bit 7-0: rx7-0 rx data in this register the last received serial data can be read. sci status register (sci_status) input register 37 (025h) read only reset value: 0000 0011 (03h) bit 7: nserr noise error 0: noise error not occurred 1: noise error occurred bit 6: frerr frame error 0: frame error not occurred 1: frame error occurred bit 5: rxf rx data register full 0: rx data register already read 1: rx data register full but not read yet bit 4: overr overrun error 0: overrun error not occurred 1: overrun error occurred bit 3: not used bit 2: r8 received 9th bit 0: rx 9th bit=0 1: rx 9th bit=1 bit 1: txem tx data register empty 0: tx data register full 1: tx data register empty bit 0: txend tx end flag 0: data transferred to the shift register 1: data transmission completed 13.4.3 sci output register. sci tx data output register (sci_out) output register 23 (017h) write only reset value: 0000 0000 (00h) bit 7-0: tx7-0 tx data in this register the serial data to be transmitted can be written. 70 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 70 nserr frerr rxf overr - r8 txem txend 70 tx7tx6tx5tx4tx3tx2tx1tx0
st52f510/f513/f514 89/137 14 i 2 c bus interface (i 2 c) 14.1 introduction the i 2 c bus interface serves as an interface between the microcontroller and the serial i 2 c bus, providing both multimaster and slave functions and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. the i 2 bus interface supports fast i 2 c mode (400khz). 14.2 main features parallel-bus/i 2 c protocol converter multi-master capability 7-bit/10-bit addressing transmitter/receiver flag end-of-byte transmission flag transfer problem detection aknowledge failure flag i 2 c master features: clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i 2 c slave features: stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag figure 14.1 i 2 c bus protocol 14.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled via software. the interface is connected to the i 2 c bus by a data pin (sda) and by a clock pin (scl). the interface can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made via software. 14.3.1 mode selection. the interface can operate in the following four modes: ? slave transmitter/receiver ? master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, providing multi-master capability. 14.3.2 communication flow. in master mode, communication flow initiates data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode the interface is capable of recognizing its own address (7 or 10-bit) and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, (msb first). the first byte following the start condition is the address (one in 7-bit mode, two in 10-bit mode), which is always transmitted in master mode.a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to figure 14.1 . scl sda 12 8 9 msb ack stop start condition condition
st52f510/f513/f514 90/137 acknowledge may be enabled and disabled via software. the i 2 c interface address and/or general call address can be selected via software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). 14.3.3 sda/scl line control. transmitter mode : the interface holds the clock line low before transmission, in order to wait for the microcontroller to write the byte in the data register. receiver mode : the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. scl frequency is controlled by a programmable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl pins must be configured as open-drain with or without pull-up. the value of the external pull-up resistance used depends on the application. 14.4 functional description by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first, the interface frequency must be configured using the related bits of the configuration registers. 14.4.1 slave mode. as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). figure 14.2 i 2 c interface block diagram data register data shift register comparator own address register (oar) clock control register (i2c_ccr) status register 1 (i2c_sr1) control register (i2c_cr) sda scl control logic status register 2 (i2c_sr2) interrupt clock control data control scl sda
st52f510/f513/f514 91/137 note: in 10-bit addressing mode, the comparison includes the header byte (11110xx0) where xx are the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledgement pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in sequence: ? acknowledge pulse if the ack bit is set. ? evf and adsl bits are set with an interrupt if the ite bit is set. afterwards, the interface waits for the i2c_sr1 register to be read, holding the scl line low (see figure 14.3 transfer sequencing ev1). next, in 7-bit mode read the i2c_in register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address sequence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following reception of the address and after the i2c_sr1 register has been read, the slave receives bytes from the sda line into the i2c_in register via the internal shift register. after each byte, the interface generates the following in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set with an interrupt if the ite bit is set. afterwards, the interface waits for the i2c_sr1 register to be read followed by a read of the i2c_in register, holding the scl line low (see figure 14.3 transfer sequencing ev2). slave transmitter following the address reception and after the i2c_sr1 register has been read, the slave sends bytes from the i2c_out register to the sda line via the internal shift register. the slave waits for a read of the i2c_sr1 register followed by a write in the i2c_out register, holding the scl line low (see figure 14.3 transfer sequencing ev3). when the acknowledge pulse is received: ? the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop condition is generated by the master. the interface detects this condition and sets: ? evf and stopf bits with an interrupt if the ite bit is set. afterwards, the interface waits for a read of the i2c_sr2 register (see figure 14.3 transfer sequencing ev4). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, releases the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note: in both cases, the scl line is not held low; however, sda line can remain low due to possible ? 0 ? bits transmitted last. at this point, both lines must be released by software. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the current byte is transferred. 14.4.2 master mode. to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent: ? the evf and sb bits are set by hardware with an interrupt if the ite bit is set. afterwards, the master waits for a read of the i2c_sr1 register followed by a write in the i2c_out register with the slave address, holding the scl line low (see figure 14.3 transfer sequencing ev5).
st52f510/f513/f514 92/137 slave address transmission at this point, the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the following event: ? the evf and add10 bit is set by hardware with interrupt generation if the ite bit is set. afterwards, the master waits for a read of the i2c_sr1 register followed by a write in the i2c_out register, holding the scl line low (see figure 14.3 transfer sequencing ev9). the second address byte is sent by the interface. after completion of this transfer (and acknowledge from the slave if the ack bit is set): ? the evf bit is set by hardware with interrupt generation if the ite bit is set. afterwards, the master waits for a read of the i2c_sr1 register followed by a write in the i2c_cr register (for example set pe bit), holding the scl line low (see figure 14.3 transfer sequencing ev6). next, the master must enter receiver or transmitter mode. note: in 10-bit addressing mode, in order to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after i2c_sr1 and i2c_cr registers have been accessed, the master receives bytes from the sda line into the i2c_in register via the internal shift register. after each byte the interface generates in sequence: ? acknowledge pulse if the ack bit is set ? evfand btf bits are set by hardware with an in- terrupt if the ite bit is set. afterwards, the interface waits for a read of the i2c_sr1 register followed by a read of the i2c_in register, holding the scl line low (see figure 14.3 transfer sequencing ev7). in order to close the communication: before reading the last byte from the i2c_in register, set the stop bit to generate the stop condition. the interface automatically goes back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last data byte received, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after the i2c_sr1 register has been read, the master sends bytes from the i2c_out register to the sda line via the internal shift register. the master waits for a read of the i2c_sr1 register followed by a write in the i2c_out register, holding the scl line low (see figure 14.3 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: ? evf and btf bits with an interrupt if the ite bit is set. in order to close the communication: after writing the last byte to the i2c_out register, set the stop bit to generate the stop condition. the interface automatically returns to slave mode (m/ sl bit cleared). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. ? arlo : detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the in- terface automatically goes back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ? 0 ? bits transmitted last. both lines must be released via software.
st52f510/f513/f514 93/137 figure 14.3 transfer sequencing 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter: 10-bit master receiver: legend: s=start, p=stop, a=acknowledge, na=non-acknowledge, s r =intermediate start without a previous sto evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading i2c_sr1 register. ev2: evf=1, btf=1, cleared by reading i2c_sr1 register followed by reading i2c_in register. ev3: evf=1, btf=1, cleared by reading i2c_sr1 register followed by writing i2c_out register. ev3-1: evf=1, af=1, btf=1, scl=0; af is cleared by reading i2c_sr2. btf is cleared by releasing the lines (stop=1,stop=0) or by readyng i2c_sr1 and writing i2c_out register (i2c_out=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. i2c_sr1 and i2c_sr2 registers can be read only after the falling edge of the ninth data clock cycle ev4: evf=1, stopf=1, cleared by reading i2c_sr2 register. ev5: evf=1, sb=1, cleared by reading i2c_sr1 register followed by writing i2c_out register. ev6: evf=1, cleared by reading i2c_sr1 register followed by writing i2c_cr (for example pe=1) ev7: evf=1, btf=1, cleared by reading i2c_sr1 register followed by reading i2c_in register. ev8: evf=1, btf=1, cleared by reading i2c_sr1, followed by writing i2c_out register or an s r . ev9: evf=1, add10=1, cleared by reading i2c_sr1 register followed by writing i2c_out register s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a ..... datan na p ev1 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7
st52f510/f513/f514 94/137 figure 14.4 event flags and interrupt generation note: the i 2 c interrupt events are connected to the same interrupt vector. they generate an interrupt if the corresponding enable control bit (ite) is set and the interrupt mask bit (mski2c) in the int_mask configuration register is unmasked (set to 1, see interrupts chapter). add10 btf adsl sb af stopf evf interrupt ite * * evf can also be set by ev6 or an error from the i2c_sr2 register. arlo berr interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no
st52f510/f513/f514 95/137 14.5 register description in the following sections describe the registers used by the i 2 c interface are described. 14.5.1 i 2 c interface configuration registers. i 2 c control register (i2c_cr) configuration register 16 (010h) read/write reset value: 0000 0000 (00h) bit 7-6: not used . they must be held to 0. bit 5: pe peripheral enable. this bit is set and cleared by software 0: peripheral disabled 1: peripheral enabled notes: ? when pe=0, all the bits of the i2c_cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 ? when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. ? to enable the i 2 c interface, write the i2c_cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4: engc enable general call this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) . 0: general call disabled 1: general call enabled note: the 00h general call address is acknowledged (01h ignored). bit 3: start generation of a start condition this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). ? in master mode 0: no start generation 1: repeated start generation ? in slave mode 0: no start generation 1: start generation when the bus is free bit 2: ack acknowledge enable this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) . 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1: stop generation of a stop condition this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). ? in master mode 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. ? in slave mode 0: no actions performed 1: release the scl and sda lines after the last byte transfer (btf=1) in slave transmitter mode. in this mode the stop bit has to be cleared by software. bit 0: ite interrupt enable 0: interrupt disabled 1: interrupt enabled i 2 c clock control register (i2c_ccr) configuration register 17 (011h) read/write reset value: 0000 0000 (00h) bit 7: fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 70 - - pe engc start ack stop ite 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0
st52f510/f513/f514 96/137 1: standard i 2 c mode (recommended up to 100 khz) 0: fast i 2 c mode (recommended up to 400 khz) bit 6-0: cc6-cc0 7-bit clock divider these bits select the speed of the bus (f scl ) depending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). the speed can be computed as follows: ? standard mode (fm/sm=1): f scl <= 100khz f scl = f cpu /(3x[cc6..cc0]+11) ? fast mode (fm/sm=0): f scl > 100khz f scl = f cpu /(2x[cc6..cc0]+9) warning: for safety reason, cc6-cc0 bits must be configured with a value >= 3 for the standard mode and >=2 for the fast mode. i 2 c own address register 1 (i2c_oar1) configuration register 18 (012h) read/write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7-1: add7-add1 interface address. these bits define the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). bit 0: add0 address direction bit. this bit is ? don ? t care ? , the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7-0: add7-add0 interface address. these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register 2 (i2c_oar2) configuration register 19 (013h) read/write reset value: 0000 0000 (00h) bit 7-3: not used bit 2-1: add9-add8 interface address. these are the most significant bits of th i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0: reserved, it must be left to 0. 14.5.2 i 2 c interface input registers. i 2 c data input register (i2c_in) input register 6 (06h) read only reset value: 0000 0000 (00h) bit 7-0: i2cdi7-i2cdi0 received data. these bits contain the byte to be received from the bus in receiver mode: the first data byte is received automatically in the i2c_in register using the least significant bit of the address. then, the next data bytes are received one by one after reading the i2c_in register. i 2 c status register 1 (i2c_sr1) input register 7 (07h) read only reset value: 0000 0000 (00h) 70 add7 add6 add5 add4 add3 add2 add1 add0 720 -----add9add8- 70 i2cdi7 i2cdi6 i2cdi5 i2cdi4 i2cdi3 i2cdi2 i2cdi1 i2cdi0 70 evf add10 tra busy btf adsl m/sl sb
st52f510/f513/f514 97/137 bit 7: evf event flag this bit is set by hardware as soon as an event occurs. it is cleared by software reading i2c_sr2 register in case of error event or as described in figure 14.3 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: ? btf=1 (byte received or transmitted) ? adsl=1 (address matched in slave mode while ack=1) ? sb=1 (start condition generated in mas- ter mode) ? af=1 (no acknowledge received after byte transmission) ? stopf=1 (stop condition detected in slave mode) ? arlo=1 (arbitration lost in master mode) ? berr=1 (bus error, misplaced start or stop condition detected) ? add10=1 address byte successfully transmitted in master mode. bit 6: add10 10 bit addressing in master mode this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading i2c_sr1 register followed by a write in the i2c_out register of the second address byte. it is also cleared by hardware when the peripheral is disabled (pe=0). 0: no add10 event occurred 1: the master has sent the first address byte bit 5: tra transmitter/receiver when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4: busy bus busy this bit is set by hardware on detection of a start condition and cleared by hardware either on detection of a stop condition or when a bus error occurs. it indicates a communication in progress on the bus. this information is not updated when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3: btf byte transfer finished this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite=1. it is cleared by software reading i2c_sr1 register followed by a read of i2c_in or write of i2c_out registers. it is also cleared by hardware when the interface is disabled (pe=0). ? following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 14.3 ). btf is cleared by reading i2c_sr1 register followed by writing the next byte in i2c_out register. ? following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading i2c_sr1 register followed by reading the byte from i2c_in register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2: adsl address matched (slave mode) this bit is set by hardware as soon as the slave address received matched with the oar register content or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software reading i2c_sr1 register or by hardware when the interface is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1: m/sl master/slave this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode
st52f510/f513/f514 98/137 bit 0: sb start bit (master mode) this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading i2c_sr1 register followed by writing the address byte in i2c_out register. it is also cleared by hardware when the interface is disabled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (i2c_sr2) input register 8 (08h) read only reset value: 0000 0000 (00h) bit 7-5: reserved. bit 4: af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading the i2c_sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3: stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading i2c_sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2: arlo arbitration lost . this bit is set by hardware when the interface loses the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by software reading i2c_sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1: berr bus error. this bit is set by hardware when the interface detects a misplaced start or stop condition. an interrupt is generated if ite=1. it is cleared by software reading i2c_sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: also a polling on busy bit has to be done to detect a bus error (busy bit cleared by hardware). bit 0: gcal general call (slave mode). this bit is set by hardware when a general call address is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 14.5.3 i 2 c interface output registers. i 2 c data output register (i2c_out) output register 6 (06h) write only reset value: 0000 0000 (00h) bit 7-0: i2cdo7-i2cdo0 data to be transmitted. these bits contain the byte to be transmitted in the bus in transmitter mode: byte transmission start automatically when the software writes in the i2c_out register. 70 - - - af stopf arlo berr gcal 70 i2cdo7 i2cdo6 i2cdo5 i2cdo4 i2cdo3 i2cdo2 i2cdo1 i2cdo0
st52f510/f513/f514 99/137 15 serial peripheral interface (spi) 15.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master, one or more slaves, or a system, in which devices may be either masters or slaves. spi is normally used for communication between the icu and external peripherals or another icu. refer to the pin description section in this datasheet for the device-specific pin-out. 15.2 main features full duplex, three-wire synchronous transfers master or slave operation four master mode frequencies maximum slave mode frequency = fckm/4. four programmable master bit rates programmable clock polarity and phase end of transfer interrupt flag write collision flag protection master mode fault protection capability. 15.3 general description spi is connected to external devices through 4 alternate pins: ? miso: master in / slave out pin ? mosi: master out / slave in pin ? sck: serial clock pin ? ss : slave select pin (if not done through soft- ware) figure 15.1 spi master slave a basic example of interconnections between a single master and a single slave is illustrated in figure 15.1 the mosi pins are connected together as the miso pins. in this manner, data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via the mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). the transmitted byte is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is complete. four possible data/clock timing relationships may be chosen (see figure 15.4 ), but master and slave must be programmed with the same timing mode. 15.4 functional description figure 15.2 shows the serial peripheral interface (spi) block diagram. this interface contains 4 dedicated registers: ? a control register (spi_cr) ? a status register (spi_status_cr) ? a data register for transmission (spi_out) ? a data register for reception (spi_in) 15.4.1 master configuration. in a master configuration, the serial clock is generated on the sck pin. 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit
st52f510/f513/f514 100/137 figure 15.2 serial peripheral interface block diagram procedure ? select the spr0, spr1 and spr2 bits to define the serial clock baud rate (see spi_cr register). ? select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 15.4 ). ? the ss pin must be connected to a high level signal during the complete byte transmit se- quence, if this pin is used. ? the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence transmit sequence begins when a byte is written in the spi_out register. the data byte is loaded in parallel into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt is generated if the spie bit is set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the spi_in register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the spi_status_cr register while the spif bit is set 2. a read to the spi_in register. note: while the spif bit is set, all writes to the spi_out register are inhibited until the spi_status_cr register is read. spi_in read buffer 8-bit shift register write read internal bus spi spie spe mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state spi_cr spi_status_cr - it request master control spr2 or ssi ssm sod spi_out
st52f510/f513/f514 101/137 15.4.2 slave configuration. in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0, spr1 and spr2 bits is not used for data transfer. procedure ? for correct data transfer, the slave device must be in the same timing mode as the master de- vice (cpol and cpha bits). see figure 15.4 . ? the ss pin must be connected to a low level sig- nal during the complete byte transmit sequence, if this pin is used. ? clear the mstr bit and set the spe bit to assign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt is generated if spie bit is set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the spi_in register is read, the spi peripheral returns the buffer value. the spif bit is cleared by the following software sequence: 1. an access to the spi_status_cr register while the spif bit is set. 2. a read to the spi_in register. note: while the spif bit is set, all writes to the spi_out register are inhibited until the spi_status_cr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 15.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the spi_out register between each data byte transfer to avoid a write collision (see section 15.4.4 ). 15.4.3 data transfer format. during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to synchronize data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when data isn ? t being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits select the data capture clock edge. figure 15.4 , shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. a write collision should not occur even if the ss pin stays low during a transfer of several bytes (see figure 15.3 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 15.3 ). in order to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its spi_out register and does not allow it to be altered. therefore, the ss pin must be high to write a new data byte in the spi_out without producing a write collision. 15.4.4 write collision error. a write collision occurs when the software tries to write to the spi_out register while a data transfer
st52f510/f513/f514 102/137 is taking place with an external device. when this occurs, the transfer continues uninterrupted; and the software writing will be unsuccessful. write collisions can occur both in master and slave mode. note: a ? read collision ? will never occur since the data byte received is placed in a buffer, in which access is always synchronous with the icu operation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device spi_out register and output the msbit on to the external miso pin of the slave device. the ss pin low state enables the slave device, but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge occurs. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device doesn ? t have a way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the spi_out register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, in order to allow the cpu to write in the spi_out register without generating a write collision. in master mode collision in the master device is defined as a write of the spi_out register, while the internal serial clock (sck) is in the process of transfer. the ss pin signal must always be high on the master device. figure 15.3 chpa/ss timing diagram wcol bit the wcol bit in the spi_status_cr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). the wcol bit is cleared by a software sequence (see section 15.5 ). 15.4.5 master mode fault. master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: ? the modf bit is set and an spi interrupt is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi peripheral. ? the mstr bit is reset, forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the spi_status_cr register while the modf bit is set. 2. a write to the spi_cr register. note: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing sequence of the modf bit. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits, while the modf bit is set (except in the modf bit clearing sequence). in a slave device the modf bit can ? t be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3
st52f510/f513/f514 103/137 figure 15.4 data clock timing diagram cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave)
st52f510/f513/f514 104/137 figure 15.5 clearing the wcol bit (write collision flag) software sequence 15.4.6 overrun condition. an overrun condition occurs when the master device has sent several data bytes and the slave device hasn ? t cleared the spif bit issued from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spi_in register returns this byte. all other bytes are lost. this condition is not detected by the spi peripheral. 15.4.7 single master and multimaster configu- rations. there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured, using an icu as the master and four icus as slaves see ( figure 15.6 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: in order to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the data byte received. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written its spi_out register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spi_cr register and the modf bit in the spi_status_cr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spi_status_cr read spi_in write spi_out 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read spi_status_cr read spi_in note: writing in spi_out regis- ter instead of reading in spi_in do not reset wcol bit read spi_status_cr or then then then
st52f510/f513/f514 105/137 figure 15.6 single master configuration 15.4.8 interrupts note: the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit (spie) and the interrupt mask bit (mskspi) in the int_mask configuration register is set. miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no
st52f510/f513/f514 106/137 15.5 spi register description in the following sections describe the registers used by the spi. 15.5.1 spi configuration registers. spi control register (spi_cr) configuration register 20 (014h) read/write reset value: 0000 0000 (00h) bit 7: spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in spi_status_cr bit 6: spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 15.4.5 master mode fault ). 0: i/o port connected to pins 1: spi alternate functions connected to pins note: the spe bit is cleared by reset, so the spi peripheral is not initially connected to the pins. bit 5: spr2 divider enable. this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 15.1 . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4: mstr master/slave mode select. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 15.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. bit 3: cpol clock polarity. this bit is set and cleared by software. this bit determines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. note: spi must be disabled by resetting the spe bit if cpol is changed at the communication byte boundaries. bit 2: cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1-0: spr1 - spr0 serial peripheral rate. these bits are set and cleared by software. used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master (see table 15.1 ). these 2 bits have no effect in slave mode. remark: it is recommended to write the spi_cr register after the spi_status_cr register when working in master mode, vice versa when working in slave mode. spi control-status register (spi_status_cr) configuration register 21 (015h) read/write reset value: 0000 0000 (00h) 70 spie spe spr2 mstr cpol cpha spr1 spr0 table 15.1 serial peripheral baud rate serial clock spr2 spr1 spr0 f ckm /2 100 f ckm /4 000 f ckm /8 001 f ckm /16 110 f ckm /32 010 f ckm /64 011 70 spif wcol or modf - sod ssm ssi
st52f510/f513/f514 107/137 bit 7: spif serial peripheral data transfer flag. (read only) this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spi_cr register. it is cleared by a software sequence (an access to the spi_status_cr register followed by a read or write to the spi_in/ spi_out registers). 0: data transfer is in progress or has been approved by a clearing sequence. 1: data transfer between the device and an external device has been completed. note: while the spif bit is set, all writes to the spi_out register are inhibited. bit 6: wcol write collision status (read only). this bit is set by hardware when a write to the spi_out register is done during a transmit sequence. it is cleared by a software sequence (see figure 15.5 ). 0: no write collision occurred 1: a write collision has been detected bit 5: or spi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spi_in register while spif = 1 (see section 15.4.6 overrun condition ). it is cleared by a software sequence (read of the spi_status_cr register followed by a read in spi_in or write of the spi_out register). 0: no overrun error. 1: overrun error detected. bit 4: modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 15.4.5 master mode fault ). an spi interrupt can be generated if spie=1 in the spi_cr register. this bit is cleared by a software sequence (an access to the spi_status_cr register while modf=1 followed by a write to the spi_cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3: not used. bit 2: sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output not disable 1: spi output disable. bit 1: ssm ss mode selection this bit is set and cleared by software. when set, it disables the alternate function of the spi slave select pin and use the ssi bit value instead of. 0: ss pin used by the spi. 1: ss pin not used (i/o mode), ssi bit value is used. bit 0: ssi ss internal mode this bit is set and cleared by software. it replaces pin ss of the spi when bit ssm is set to 1. ssi bit is active low slave select signal when ssm is set to 1. 0 : slave selected 1 : slave not selected. remark: it is recommended to write the spi_cr register after the spi_status_cr register when working in master mode, vice versa when working in slave mode. 15.5.2 spi input register. spi data input register (spi_in) input register 5 (05h) read only reset value: 0000 0000 (00h) bit 7-0: spidi7-spidi0 received data. the spi_in register is used to receive data on the serial bus. note: during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. 70 spidi7 spidi6 spidi5 spidi4 spidi3 spidi2 spidi1 spidi0
st52f510/f513/f514 108/137 warning: a read to the spi_in register returns the value located in the buffer and not the contents of the shift register (see figure 15.2 ). 15.5.3 spi output register. spi data output register (spi_out) output register 5 (05h) write only reset value: 0000 0000 (00h) bit 7-0: spido7-spido0 data to be transmitted. the spi_out register is used to transmit data on the serial bus. in the master device only a write to this register will initiate transmission/reception of another byte. warning: a write to the spi_out register places data directly into the shift register for transmission. 70 spido7 spido6 spido5 spido4 spido3 spido2 spido1 spido0
st52f510/f513/f514 109/137 16 electrical characteristics 16.1 parameter conditions unless otherwise specified, all voltages are referred to v ss. 16.1.1 minimum and maximum values. unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of environment temperature, supply voltage and frequencies by tests in production on 100% of the devices with an environmental temperature at t a =25 c and t a =t a max (given by the selected temperature range). data are based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. the minimum and maximum values are based on characterization and refer to sample tests, representing the mean value plus or minus three times the standard deviation (mean 3 ). figure 16.1 pin loading conditions 16.1.2 typical curves. unless otherwise specified, all typical curves are provided only as design guidelines and are not tested. 16.1.3 typical values. unless otherwise specified, typical data is based on t a =25 c, v dd =5v. they are provided only as design guidelines and are not tested. 16.1.4 loading capacitor. the loading condition used for pin parameter measurement is illustrated in figure 16.1 . 16.1.5 pin input voltage. input voltage measurement on a pin of the device is described in figure 16.2 figure 16.2 pin input voltage st52 pin c l st52 pin v in
st52f510/f513/f514 110/137 16.2 absolute maximum ratings stresses above those listed as ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 16.1 voltage characteristics symbol ratings max values unit v dd -v ss supply voltage 6.5 v v in input voltage on any pin 1) 2) v ss -0.3 to v dd +0.3 v desd electrostatic discharge voltage 2000 table 16.2 current characteristics symbol ratings max values unit i vdd total current in v dd power lines (source) 3) 100 ma i vss total current in v ss ground lines (sink) 3) 100 i io output current sunk by any standard i/o and control pin 20 output current source by any i/os and control pin -20 injected current on reset pin 5 i inj(pin) 2) injected current on oscin and oscout pins 5 injected current on any other pin 4) 5 i inj(pin) total injected current (sum of all i/o and control pins) 4) 20 table 16.3 thermal characteristics symbol ratings max values unit t stg storage temperature range -65 to +150 c t j maximum junction temperature 150 notes: 1. connecting i/o pins directly to vdd or vss could damage the device if the unintentional internal reset is generated or an unexpected change of i/o configuration occurs (for example, due to the corrupted program counter). in order to guarantee safe operation, this connection has to be performed via a pull- up or pull-down resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same manner to vdd or vss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, other- wise refer to iinj(pin) specification. a positive injection is induced by vin>vdd while a negative injec- tion is induced by vinvdd while a negative injection is induced by vin st52f510/f513/f514 111/137 16.3 operating conditions operating condition: t a =-40 to 85 c (unless otherwise specified). notes: 1. it is recommendend to insert a capacitor beetwen v dd and v ss for improving noise rejection. recom- mended values are 10 f (electrolytic or tantalum) and/or 100 nf (ceramic). figure 16.3 fosc maximum operating frequency versus vdd supply table 16.4 operating conditions symbol parameter test condition min. max unit v dd operating supply voltage in working mode f osc = 1 to 20mhz 2.8 5.5 v operating supply voltage in isp mode f osc = 1 to 20mhz 2.8 5.5 operating supply voltage in iap mode f osc = 1 to 20mhz 2.8 5.5 t a ambient temperature range -40 85 c f osc 1) external clock frequency 1 20 mhz tbd 0 0.5 1 1.5 2 2.7 3 3.5 4 4.5 5 5.5 10 20 functionality not guaranteed in this area functionality guaranteed in this area vdd (v) f osc. max (mhz) 1 2.8 6 functionality guaranteed in this area from 0c to 85c
st52f510/f513/f514 112/137 16.4 supply current characteristics supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test condition in run mode for all the i dd measurements are, unless otherwise specified: oscin = external square wave, from rail to rail; oscout = floating; all i/o pins in input to vss t a =-40 to 85 c notes: 1. cpu running with memory access, all i/o pins in input mode with a static value at v ss (no load), all pe- ripherals switched off; clock input. 2. cpu in wait mode with all i/o pins in input mode with a static value at v ss (no load), all peripherals switched off; clock input. 3. cpu running with memory access, all i/o pins in input mode with a static value at v ss (no load), all pe- ripherals switched off; clock input, cpu clock frequency divided 64 times by using the related configu- ration register. 4. device driven by internal oscillator at 10 mhz. 5. not tested in production table 16.5 supply current in run, wait and slow mode, 5,5 v supply voltage 5) . symbol parameter conditions typ max 3) unit i dd supply current in run mode 1) v dd =5.5v ma f osc =1 mhz 3.75 f osc =5 mhz, 4.50 f osc =10 mhz 6.5 f osc =20 mhz 10.90 f intosc =10 mhz 5.60 4) supply current in wait mode 2) f osc =1 mhz 2.50 f osc =5 mhz 2.85 f osc =10 mhz 4.00 f osc =20 mhz 5.55 f intosc =10 mhz 2.70 4) supply current in slow mode 3) v dd =5.5v f cpu =f osc /64 f osc =1 mhz 3.70 f osc =5 mhz 4.25 f osc =10 mhz 5.20 f osc =20 mhz 8.10 f intosc =10 mhz 4.20 4)
st52f510/f513/f514 113/137 notes: 1. cpu running with memory access, all i/o pins in input mode with a static value at v ss (no load), all pe- ripherals switched off; clock input. 2. cpu in wait mode with all i/o pins in input mode with a static value at v ss (no load), all peripherals switched off; clock input. 3. cpu running with memory access, all i/o pins in input mode with a static value at v ss (no load), all pe- ripherals switched off; clock input, cpu clock frequency divided 64 times by using the related configu- ration register. 4. device driven by internal oscillator at 10 mhz. 5. not tested in production. notes: 1. all i/o pins in input mode with a static value at v ss (no load), plvd switched off. 2. not tested in production table 16.6 supply current in run, wait and slow mode, 2.8 v supply voltage 5) . symbol parameter conditions typ max 3) unit i dd supply current in run mode 1) v dd =2.8v ma f osc =1 mhz 2.60 f osc =5 mhz, 3.50 f osc =10 mhz 5.00 f osc =20 mhz 9.10 f intosc =10 mhz 5.00 4) supply current in wait mode 2) f osc =1 mhz 1.80 f osc =5 mhz 2.20 f osc =10 mhz 2.70 f osc =20 mhz 4.10 f intosc =10 mhz 2.40 4) supply current in slow mode 3) v dd =2.8v f cpu =f osc /64 f osc =1 mhz 2.45 f osc =5 mhz 2.85 f osc =10 mhz 4.20 f osc =20 mhz 6.35 f intosc =10 mhz 3.65 4) table 16.7 supply current in halt mode 2) . symbol parameter conditions typ max unit i dd supply current in halt mode 1) vdd = 5.5 v 13.5 a vdd = 2.8 v 9.5
st52f510/f513/f514 114/137 figure 16.4 typical idd in run vs fosc figure 16.5 typical idd in wait vs fosc vdd (v) 12 10.5 9 7.5 6 4.5 3 1.5 0 2.7 3.2 3.7 4.2 4.7 5.2 5mhz 10mhz 20mhz 1mhz idd (ma) 0 1,5 3 4,5 6 2,7 3,2 3,7 4,2 4,7 5,2 vdd (v) idd (ma) 5mhz 10mhz 20mhz 1mhz
st52f510/f513/f514 115/137 16.5 clock and timing characteristics operating conditions: v dd =2.8 v to 5.5 v, ta=-40 to 85 c, unless otherwise specified. values by design. 16.6 power on reset 1. measured with v dd slope = 0.05 v/s. internal reset is released if v dd goes above v por . notice that there is not hysteresis on por. 2. suggested v dd slope for correct working of the device. not tested in production. table 16.8 general timing parameters symbol parameters test condition min typ. max unit f osc oscillator frequency 1 20 mhz t wint minimum external interrupt pulse width 2 cpu clock cycle t inst instruction time 4 8 16 t int interrupt reaction time 12 20 28 table 16.9 power on reset symbol parameter conditions min typ max unit v por power on reset 1) ta=25 c 2.55 2.56 2.70 v v ddslp v dd slope 2) ta=25 c 0.05 1000 v/s
st52f510/f513/f514 116/137 16.7 memory characteristics operating conditions: v dd =2.8 v to 5.5 v, ta=-40 to 85 c, unless otherwise specified. notes: 1. minimum v dd supply voltage that avoids the loosing of data stored into ram or into hardware registers. below the specified threshold the device is turned off and it is turned on only after the v dd goes above the por threshold, as consequence the device is reset by the por and the ram is put to all 0. guar- anteed by design, not tested in production. 2. flash/eeprom can be programmed at signle byte or at 32 bytes blocks. in working mode (in applica- tion programming) the time includes the erase operation before the writing. 3. the data retention time increases when the t a decreases. 4. not tested in production, guaranteed by design. table 16.10 ram and registers symbol parameter conditions min. typ. max unit v rm data retention mode 1) plvd disabled v ddmin v table 16.11 flash program/data memory symbol parameter conditions min. typ. max unit t prog programming time for 1/32 bytes 2) v dd = 2.8 v - 5.5 v virgin flash isp mode 2.5 ms programming time for 1/32 bytes 2) v dd = 2.8 v - 5.5 v not virgin flash iap mode 5 programming time for 8 kbytes v dd = 2.8 v - 5.5 v fast programming mode isp mode 640 t ret data retention 3) t a =55 c 10 years n rw write/erase cycles t a =25 c tbd cycle table 16.12 eeprom data memory symbol parameter conditions min. typ. max unit t prog programming time for 1/32 bytes 2) t a =25 c 5ms t ret data retention 3) t a =55 c 10 years n rw write/erase cycles t a =25 c tbd cycle
st52f510/f513/f514 117/137 16.8 programmable low voltage detector (plvd) operating conditions: v dd =2.8 v to 5.5 v, ta= 25 c, unless otherwise specified. notes: 1. measured with v dd slope in the range from 0.2 v/s to 4000 v/s . 2. duration of the glitch not detected by the plvd. values by design, not tested in production. 16.9 internal oscillator the frequency of the internal oscillator is centered at 10 mhz but can be subject to variation due to process spread: this may be calibrated by using the related option byte. operating conditions: v dd =2.8 v to 5.5 v, ta=-40 to 85 c, unless otherwise specified. notes: 1. drift values in temperature are referred to t a =25 c internal oscillator frequency value. symbol parameter conditions min typ max unit v lvdt+ reset release threshold (v dd rise) 1) high threshold 4.18 4.22 4.33 v medium threshold 3.64 3.70 3.76 low threshold 3.05 3.11 3.15 v lvdt- reset threshold (v dd fall) 1) high threshold 3.83 3.96 3.96 medium threshold 3.30 3.40 3.46 low threshold 2.77 2.85 2.87 t g filtered glitch on v dd 2) not detected by the plvd 50 int. clock cycle symbol parameter conditions min typ max unit f oscint internal operating frequency t a = 25 c, v dd =5.5 v not calibrated 10 mhz thdr osc thermal drift of the internal oscillator 1) t a = -40 c 12 % t a = 0 c 3 t a = 85 c 2 f cal step of calibration t a = 25 c 100 khz
st52f510/f513/f514 118/137 16.10 port pin characteristics 16.10.1 general characteristics operating conditions: v dd =2.8 v to 5.5 v, ta=-40 to 85 c, unless otherwise specified. notes: 1. typical data are based on t a =25 c and v dd =5.5 v 2. data from characterization. not tested in production. 3. hysteresis voltage between schmitt trigger switching level. data by design. 4. values of the pull-up resistrors depends on v dd (see figure 16.7 ). 5. data based on design simulation and/or technology characteristics, not tested in production. figure 16.6 level input schmitt trigger 5) figure 16.7 internal pull-up resistor vs vdd 5) symbol parameter condition min typ 1) max unit v il input low level voltage 2) 1.2 v v ih input high level voltage 2) 1.7 v hys schmitt trigger voltage hysteresis 3) 0.5 i l input leakage current 2) v ss v in v dd 1 a r pu internal pull-up resistor 4) v dd = 2.8 v to 5.5 v 13.6 15.5 31.5 k ? r s input protection resistor 5) 0.3 t f(io)out output high to low level fall time 5) c l = 50 pf between 10% and 90% 5 ns t r(io)out output low to high level rise time 5) 5 t w(it)in external interrupt pulse time 5) 2 cpu clock cycle 0.5 1.5 2.5 0 1 2 3 4 5 v = 5v dd t = 25 c a (typical) v (v) o v (v) i 1.7 1.2 r pull up @ t=25 o c 10 12 14 16 18 20 22 24 26 28 2,7 3,2 3,7 4,2 4,7 5,2 r pull up (k ohm) vdd (v)
st52f510/f513/f514 119/137 figure 16.8 port pin equivalent circuit 16.10.2 output driving current operating conditions: v dd =2.8 v to 5.5 v, ta=25 c, unless otherwise specified. table 16.14 output voltage levels for class b pins 3) notes: 1. the i io sunk current must always respect the absolute maximum rating specified in section 16.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . data from characterization; not tested in production. 2. the i io sourced current must always respect the absolute maximum rating specified in section 16.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . data from characterization; not tested in production. 3. class a indicates an 8 ma driving capability of the output buffer while class b indicates a 4 ma driving capability of the output buffer. see general description chapter for a complete description of class a and b pins for every package. table 16.13 output voltage levels for class a pins 3) symbol parameter conditions min typ max unit v ol 1) output low level voltage for standard i/o pin when 8 pins are sunk at same time. i io =+8ma v dd = 2.8 v 0.41 0.43 v v oh 2) output high level voltage for standard i/o pin when 8 pins are sourced at same time. i io =- 8ma v dd = 2.8 v 2.33 2.35 symbol parameter conditions min typ max unit v ol 1) output low level voltage for standard i/o pin when 8 pins are sunk at same time. i io =+4ma v dd = 2.8 v 0.25 0.33 v v oh 2) output high level voltage for standard i/o pin when 8 pins are sourced at same time. i io =- 4ma v dd = 2.8 v 2.42 2.45
st52f510/f513/f514 120/137 16.11 control pins characteristics 16.11.1 reset pin. operating conditions: v dd =2.8 v to 5.5 v, ta=25 c, unless otherwise specified. notes: 1. data by design, not tested in production. 2. hysteresis voltage between schmitt trigger switching level. based on simulation results not tested in production. 3. max duration of the noise that is filtered by the pin. data by design, not tested in production. 4. measures at ta=-40 c to 85 c, typical data are based on t a =25 c and v dd =5.5 v. values of the pull- up resistors depends on v dd . 16.11.2 v pp pin. operating conditions: v dd =2.8 v to 5.5 v, ta=25 c, unless otherwise specified. notes: 1. in working mode v pp must be tied to v ss 2. data is based on design simulations, not tested in production. table 16.15 reset pin symbol parameter conditions min typ max unit v il input low level voltage 1) v dd = 2.8 v 1.18 v v dd = 5.5 v 2.34 v ih input high level voltage 1) v dd = 2.8 v 1.63 v dd = 5.5 v 3.22 v hys schmitt trigger voltage hysteresis 2) v dd = 2.8 v 0.45 t fn duration of noise 3) 100 ns t rst reset pulse duration 1) 500 r pures pull-up resistor 4) v dd = 2.8 v to 5.5 v 13.9 15.8 29.7 k ? table 16.16 v pp 1) pin symbol parameter conditions min typ max unit v il input low level voltage 2) v dd = 2.8 v 1.18 v v dd = 5.5 v 2.34 v ih input high level voltage 2) v dd = 2.8 v 1.63 v dd = 5.5 v 3.22
st52f510/f513/f514 121/137 16.12 emc characteristics susceptibility tests are performed on a sample basis during product characterization. 16.12.1 functional ems . (electro magnetic susceptibility) based on a simple running application on the product (toggling two leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operation to be resumed. notes: 1. data based on characterization results, not tested in production. 2. it is suggested to insert decoupling capacitors (10 nf and 100 nf electrolytic) on the power supply lines to obtain a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. 16.12.2 absolute electrical sensitivity. based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 16.12.3 electro-static discharge (esd). electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pincombination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). the model imulated is the human body model. this test conforms to the jesd22- a114a/a115a standard. see figure 16.9 . figure 16.9 typical equivalent esd circuits symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd =5 v, t a =25 c , f osc = 8 mhz sdip32 conform with iec 1000-4-2 2b v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd =5 v, t a =25 c , f osc = 8 mhz sdip32 conform with iec 1000-4-4 3b symbol parameter conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a =25 c 2kv st five s2 high voltage pulse generator s1 r = 1500 ? c l = 100 pf human body model high voltage pulse generator
st52f510/f513/f514 122/137 16.12.4 static and dynamic latch-up. lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. dlu: electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 16.10 . figure 16.10 simplified diagram of the esd generator for dlu notes: 1. class description: class a is an stmicroelectronics internal specification. all its limits are higher than the jedec specification, that means when a device belongs to class a it exceeds the jedec standard. class b strictly covers all the jedec criteria (international standard). 16.12.5 esd pin protection strategy. in order to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. stress generally affects the circuit elements, which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements that are to be protected must not receive excessive current, voltage, or heating within their structure. an esd network combines the different input and output protections. this network works by allowing safe discharge paths for the pins subject to esd stress. two critical esd stress cases are presented in figure 16.11 and figure 16.12 for standard pins. standard pin protection in order to protect the output structure the following elements are added: - a diode to v dd (3a) and a diode from v ss (3b) - a protection device between v dd and v ss (4) in order protect the input structure the following elements are added: - a resistor in series with pad (1) - a diode to v dd (2a) and a diode from v ss (2b) - a protection device between v dd and v ss (4) symbol parameter conditions class 1) lu static latch-up class t a =25 c t a =85 c a a dlu dynamic latch-up class v dd =5.5v, f osc = 8 mhz, t a =25 c a st five v dd v ss discharge tip hv relay discharge return connection esd generator r d = 330 ? r ch = 50 m ? c s = 150 pf
st52f510/f513/f514 123/137 figure 16.11 safe discharge path subjected to esd stress figure 16.12 negative stress on a standard pad vs. vdd out (4) in vdd vss vdd vss (2a) (2b) (3a) (3b) (1) main path path to avoid main path vss vdd out (3b) (4) in (3a) (2b) (1) vss (2a) vdd
st52f510/f513/f514 124/137 16.13 i 2 c interface characteristics subject to general operating conditions for v dd , f osc , and t a, unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). the i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 16.13 i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirements, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefinited region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of the scl signal. 4. measurement points are done at levels: 0.3xv dd and 0.7xv dd . table 16.17 i 2 c interface characteristics symbol parameter standard mode i 2 cfast mode i 2 c unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ns t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ms c b capacitive load for each bus line 400 400 pf
st52f510/f513/f514 125/137 16.14 spi characteristics subject to general operating conditions for v dd , f osc , and t a, unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss, sck, mosi, miso ). figure 16.14 spi slave timing diagram with cpha = 0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when the spi is disabled it has its alternate function capability released. in this case, the pin status de- pends on the i/o port configuration. 3. measurement points are done at levels: 0.3xv dd and 0.7xv dd . symbol parameter condition min max unit f sck spi clock frequency master f cpu /128 f cpu /4 mhz slave 0 f cpu /4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss) ss setup time slave 120 ns t h(ss) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 clk cycle t h(mo) data output hold time 0.25
st52f510/f513/f514 126/137 figure 16.15 spi slave timing diagram with cpha = 0 3) figure 16.16 spi master timing diagram notes: 1. measurement points are done at levels: 0.3xv dd and 0.7xv dd . 2. when the spi is disabled it has its alternate function capability released. in this case, the pin status de- pends on the i/o port configuration.
st52f510/f513/f514 127/137 16.15 10-bit adc characteristics operating conditions: v dd =2.8 v to 5.5 v, ta=-40 to 85 c, unless otherwise specified. notes: 1. data by design. they are given only as design guidelines and are not tested. 2. when v ref is selected as internal it corresponds to v dd . when vref is external it must be <= v dd and >=v ss , and channel 0 cannot be used because ain0 pin is the input for v ref . 3. any added external serial resistor will downgrade the adc accuracy. data by design, not tested in production. 4. approximated value corresponding to about 20 conversion cycles, that is recommended at a/d start-up to ensure a correct conversion. table 16.18 adc accuracy with v dd =5.0 v notes: 1. data based on characterization results over the whole temperature range, monitored in production. symbol parameter conditions min typ 1) max unit f adc adc clock frequency min=slow mode max=fast mode, ta=25 f oscint /12 f oscint / 6 mhz v ref external reference voltage 2) v ss v dd v r ain external input resistor 400 3) ? r adc internal input resistor 1.0 k ? c adc internal sample and hold capacitor 9 pf t stab stabilization time after adc enable slow mode = 800 khz 400 4) s t load sample capacitor loading time 600 ns t conv conversion time 20 s t stab stabilization time after adc enable fast mode = 1600 khz 200 4) s t load sample capacitor loading time 600 ns t conv conversion time 10 s symbol parameter conditions typ max unit |e t | total unadjusted error 1) v dd =5v, ta=-40 to 85 c typical values at ta=25 c 4.5 lsb e o offset error 1) 11.8 |e g |gain error 1) 35 |e d | differential linearity error 1) 2.5 3.5
st52f510/f513/f514 128/137 figure 16.17 adc accuracy characteristics e o e g 1lsb ideal 1lsb ideal v ref v ss ? 1024 ----------------------------------- = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dda v ssa
st52f510/f513/f514 129/137 17 package characteristics 17.1 so16 package data table 17.1 so16 package mechanical data dim mm inch. min typ. max min typ. max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 h 10.00 10.65 0.394 0.419 e 1.27 0.050 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n16 h e c h x 45 a l b e a1 a d
st52f510/f513/f514 130/137 17.2 so20 package data table 17.2 so20 package mechanical data dim mm inch. min typ. max min typ. max a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 0 8 0 8 eh a a1 b e d c h x 45 l
st52f510/f513/f514 131/137 17.3 pdip20 package data table 17.3 pdip20 package mechanical data dim mm inch. min typ. max min typ. max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.16 26.92 0.980 1.030 1.060 d1 0.13 0.005 e 2.54 0.100 eb 10.92 0.430 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n20 e1 d b e a a1 l a2 c eb 11 10 1 20 b2
st52f510/f513/f514 132/137 17.4 so28 package data table 17.4 so28 package mechanical data dim mm inch. min typ. max min typ. max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 17.70 18.10 0.697 0.713 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n28 h x 45 c l a a1 e b d h e l
st52f510/f513/f514 133/137 17.5 sdip32 package data table 17.5 sdip32 package mechanical data dim mm inch. min typ. max min typ. max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 n32 d b2 b e a a1 a2 l e1 e ec c ea eb
st52f510/f513/f514 134/137 17.6 lfbga36 package data table 17.6 lfbga36 package mechanical data dim mm inch. min typ. max min typ. max a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 5.750 6.000 6.150 0.226 0.236 0.242 d1 4.000 0.157 e 5.750 6.000 6.150 0.226 0.236 0.242 e1 4.000 0.157 e 0.720 0.800 0.880 0.028 0.031 0.035 f 0.850 1.000 1.150 0.033 0.039 0.045 ddd 0.120 0.005
st52f510/f513/f514 135/137 18 important notes 18.1 silicon identification this document describes the limitations that apply to st52f510/f513/f514 devices, silicon revision u. this is identifiable on: device package, by the last letter of trace code marked on device package. on the box, by the last 3 digits of the internal sales type printed on the box label. 18.2 silicon limitations 18.2.1 eeprom writing error flag. description when an instruction for writing data ("lder") is located in a write protected page, (clearly to write data in an unprotected page of program/data memory) the writing error flag bit 1: prtcd page protected of iap status register (iap_sr) [input register 40 (028h)] is always set even if the writing is successful. workaround once the prtcd bit is set it is anyway possible to verify the correct writing of a data byte reading the target location with the instruction "ldre" and comparing it with the data byte intended to store. 18.2.2 cpu prescaler after reset. description the reset caused by the watchdog does not reset the cpu prescaler configuration register cpl_clk [configuration register 46 (02eh)] so the cpu continues to run with the frequency used before the reset. workaround software workaround can be used: if the user thinks that a watchdog reset is possible, he should take care of writing the cpu prescaler configuration register as first instruction after a wdg reset. 18.2.3 sci synchronization in case of consecu- tive bytes reception. description . the sci looses synchronization in data reception when two bytes are received consecutively, without an idle time of at least 3/16 of bit time (3 sci clock_rx cycles). workaround . to avoid lost of synchronization when two consecutive bytes are received by the sci, an idle time corresponding to 3 clock_rx cycles must be guaranteed between the stop bit of each byte and the start bit of the successive byte by the transmitter device. as an implementation suggestion, this can be achieved by configuring the external transmitter device with 2 stop bits and the st5 sci configured as a receiver with 1 stop bit. 18.2.4 i2c general call flag. description . the general call flag, bit0 on i2c status register 2 (i2c_sr2) [input register 8 (08h)] is not reset if a second start condition occurs without a stop condition or if the peripheral is not disabled setting to zero bit5, pe peripheral enable, on i2c control register (i2c_cr) [configuration register 16 (010h)]. workaround . none. the user has to guarantee that every communication (start condition) ends with a stop condition. 18.2.5 halt not skipped. description . when the hardware wdt is enabled, if halt instruction is preceded by wdtslp instruction or if none of wdtslp and wdtrfr instruction occurred, halt is not skipped. workaround . the user should avoid using halt instruction when hardware watchdog is used. part number trace code marked on device internal sales type on box label st52f51yxxxx ? xxxxxxxxxu ? 52f51yxxxx$uz 52f51yxxxx$a3 legend: y= 0,3,4; z= 3,4,5
st52f510/f513/f514 136/137 19 revision history table 19.1 date revision description of changes april 04 2.1 table 4.1 sales type memory organization on page 34 modified table 4.3 error codes on page 40 modified section 5.6 register description on page 45 high priority register (int_prl_h) (prl24-prl0) became (prl23-prl0) section 12.6.2 pwm/timer 1 input registers on page 81 pwm/timer 1 status register (pwm1_status) bit description modified section 13.4.3 sci output register on page 88 row 2 ? input register ? became ? output register ? section 14.3.2 communication flow on page 89 small modifications ta b l e i n section 16.12.1 functional ems on page 121 changed, note 2 eliminated section 16.12.3 electro-static discharge (esd) on page 121 changed ta b l e i n section 16.12.3 electro-static discharge (esd) on page 121 changed figure 16.9 typical equivalent esd circuits on page 121 modified chapter 18 important notes on page 135 added chapter 19 revision history on page 136 added april 04 2.2 figure 3.2 program/data memory organization on page 25 modified section 12.5.1 pwm/timer 0 configuration registers on page 77 modified (strmod, resmod, respol) description may 04 2.3 all hyperlink coloured in blue document pagination modified all references to rc external oscillator removed section 14.5.2 i2c interface input registers on page 96 ? bit 4: busy bus busy ? modified. ? bit 1: berr bus error ? added note
137/137 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publicatio n are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2004 stmicroelectronics ? printed in italy ? all rights reserved stmicroelectronics group of companies australia - brazil - china - canada - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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